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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM20027/D ImageMOS Advance Information Color SXGA Digital Image Sensor 1280 x 1024 pixel progressive scan solid state image sensor with integrated CDS/PGA/ADC, digital programming, control, timing, and pixel correction features Features: * * * * * * * * * * * * * * * * * * SXGA resolution, active CMOS image sensor with square pixel unit cells 6.0m pitch pixels with patented pinned photodiode architecture Bayer-RGB color filter array with optional micro lenses High sensitivity, quantum efficiency, and charge conversion efficiency Low fixed pattern noise / Wide dynamic range Part Number Antiblooming and continuous variable speed shutter Single master clock operation MCM20027IBBL Digitally programmable via I2C interface Integrated on-chip timing/logic circuitry CDS sample and hold for suppression of low frequency MCM20027IBMN and correlated reset noise 20X programmable variable gain to optimize dynamic range and facilitate white balance and iris adjustment 10-bit, pipelined algorithmic RSD ADC (DNL +0.5 LSB, INL +1.0 LSB) Automatic column offset correction for noise suppression Pixel addressability to support `Window of Interest' windowing, resolution, and subsampling Encoded data stream 10 fps full SXGA at 13.5MHz Master Clock Rate Single 3.3V power supply 48 pin CLCC package MCM20027 1.3 Megapixel Description Color RGB sensor with Lenslets Monochrome sensor without Lenslets Package 48 Pin CLCC 48 Pin CLCC The MCM20027 is a fully integrated, high performance CMOS image sensor with features such as integrated timing, control, and analog signal processing for digital imaging applications. The part provides designers a complete imaging solution with a monolithic image capture and processing engine thus making it a true "camera on a chip". System benefits enable design of smaller, portable, low cost and low power systems. Thereby making the product suitable for a variety of consumer applications including still/full motion imaging, security/surveillance, and automotive among others. The imaging pixels are based on active CMOS pixels using pinned photodiodes that are realized using Motorola's sub-micron ImageMOSTM technology. A maximum frame rate of 10 FPS at full resolution can be achieved, further the frame rate is completely adjustable without adjusting the system clock. Each pixel on the sensor is individually addressable allowing the user to control "Window of Interest" (WOI) panning and zooming. Control of sub-sampling, resolution, exposure, gain, and other image processing features is accomplished via a two pin I2C interface. The sensor is run by supplying a single Master Clock. The sensor output is 10 digital bits providing wide dynamic range images. ELECTRO STATIC DISCHARGE WARNING: This device is sensitive to electrostatic discharge (ESD).ESD immunity meets Human Body Model (HBM) < 1500 V and Machine Model (MM) < 150 V Additional ESD data upon request. When handling this part, proper ESD precautions should be followed to avoid exposing the device to discharges which may be detrimental to its immediate performance and/or reduce the parts expected lifetime.. This document contains information on a new product.Specifications and information herein are subject to change without notice. (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 1 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Specifications Image Size: 7.7mm x 6.1mm (9.82mm Diagonal, 1/2" Optic) Resolution:1280 x 1024 pixels, available digital zoom and region of interest (ROI) windowing Pixel Size: 6m x 6m Monochrome Sensitivity: 1.8 V/Lux-sec Min. Detectable Light Level: 3 Lux at 10FPS/F2 lens Scan Modes: Progressive Shutter Modes: Continuous Frame and Single Frame Rolling Shutter modes available Readout Rate: 13.5MSPS Frame Rate: 0-10 Full frames (1280x1024) per second Max Master Clock Frequency: 13.5MHz System Dynamic Range: 50dB On Chip programmable gain: -9.5dB to 26dB On Chip Image Correction: Column Fixed Pattern Correction Analog to Digital Converter: 10-bit, RSD ADC (DNL +/-0.5 LSB, INL +/-1.0 LSB) Power Dissipation: 250mW RMS, operating @13.5Mhz Package: 48 pin ceramic LCC Temperature Operating Range: 0-40oC MCLK INIT 1280 x 1024 pixels (1296 x 1048 total including dark and isolation) Digital Control Sensor Interface I2C Serial Interface STROBE SYNC SCLK SDATA CDS Post ADC Column Offset White Balance Global Gain Global Offset ADC(9:0) HCLK FRC 10 Bit ADC Control Signal Encoding VCLK SOF Figure 1. MCM20027 Simplified Block Diagram MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 2 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 1296 4Dark + 4Isolation SOF VCLK HCLK STROBE 48 Master Row Sequencer, Integration Control, and Timing generator 44 45 47 4Dark +4Isolation 4Da rk +4Is olati on 104 8 Roe Decoder and Drivers 1024 Image Sensor Pixel Array 1280 2 1 12 12Dark +4Isolation Column Sequencer & Drivers Column Decode, Sensing, and Muxing 1 INIT Color Sequencer Analog Switch 6 6 6 6 I2 C Serial Interface 30 29 SDATA SCLK 43 MCLK EXT_VINR 10 Colum n Offset Calibration 6 6 6 6 I C Register Decode 2 EXT_VINS 11 42 Frame Rate Clamp WB PGA 0.88x - 2.84x Global PGA 0.696x - 7.48x ADC9 ADC8 ADC7 ADC6 ADC5 Column DOVA 1.5x Global Dova 1 0 Bit 2.0x RSD Pip elin ed ADC 41 40 39 10 38 35 ADC4 CLRCA CLRCB CVREFM CVREFP EXTRES EXTRESRTN 6 7 P ost ADC P rocessing Bandgap Reference and Bias Generation 34 Test Monitor Logic 10 ADC3 ADC2 ADC1 ADC0 33 32 31 14 15 20 19 V refp V refm V cm I bias Analog Circuits Digital Logic 16 VAG 17 VAGTRN 18 VAGREF 21 CVBG See "MCM20027 Pin Definitions" on page 67 for more information Figure 2. MCM20027 Detailed Block Diagram Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 3 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Table Of Contents 1.0 2.0 2.1 2.2 3.0 3.1 3.2 4.0 5.0 6.0 6.1 6.2 6.3 6.4 6.5 7.0 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.5 7.6 8.0 8.1 8.2 MCM20027 Overview...................................................................... MCM20027 Architecture................................................................. Pixel Architecture........................................................................... Color Separation and Fill Factor Enhancement .......................... Frame Capture Modes.................................................................... Continuous Frame Rolling Shutter capture mode (Default)........ Single Frame Rolling Shutter capture mode (SFRS)................... Active Window of Interest Control ................................................ Active Window Sub-sampling Control.......................................... Frame Rate and Integration Time Control.................................... CFRS Frame Time/Rate:................................................................. Integration Time in CFRS mode:................................................... SFRS Frame Time/Rate:................................................................. Integration Time in SFRS mode.................................................... Example of Frame time/rate and Integration Time in CFRS and SFRS modes.................................................................................... Analog Signal Processing Chain Overview ............................... Correlated Double Sampling (CDS)............................................... Frame Rate Clamp (FRC)................................................................ Programmable Per-Column Offset .............................................. Digitally Programmable Gain Amplifiers (DPGA) for White Balance and Exposure Gain................................................................ White Balance Control PGA........................................................... Exposure Global Gain PGA............................................................ Gain Modes..................................................................................... Global Digital Offset Voltage Adjust (DOVA)................................ Analog to Digital Converter (ADC)................................................ MCM20027 Sensor External Controls........................................... Initialization .................................................................................... Standby Mode............................................................................... 7 7 7 9 10 10 11 12 12 13 13 13 14 14 15 15 15 16 16 16 16 17 19 19 20 20 20 MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 4 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Table Of Contents 8.3 8.4 8.5 8.6 9.0 9.1 9.2 9.3 9.4 9.5 10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 11.0 12.0 12.1 13.0 14.0 15.0 16.0 17.0 Tristate Mode.................................................................................. References CVREFP, CVREFM...................................................... Common Mode References: VAG, VAGREF and VAGRETURN. Internal Bias Current Control......................................................... Sensor Output/Input Signals......................................................... Start Of Data Capture (SYNC)........................................................ Start Of Row Readout (SOF).......................................................... Horizontal Data SYNC (VCLK)........................................................ Data Valid (HCLK)........................................................................... Strobe Signal................................................................................... I2C Serial Interface.......................................................................... MCM20027 I2C Bus Protocol ........................................................ START Signal.................................................................................. Slave Address Transmission......................................................... Acknowledgment ........................................................................... Data Transfer.................................................................................. Stop Signal...................................................................................... Repeated START Signal................................................................. I2C Bus Clocking and Synchronization........................................ Register Write................................................................................. Register Read.................................................................................. Suggested Software Register Changes........................................ MCM20027 Utility Programming Registers................................... Register Reference Map ................................................................ Detailed Register Block Assignments.......................................... Electrical Characteristics .............................................................. MCM20027 Pin Definitions............................................................. MCM20027 Packaging Information................................................ MCM20027 Typical electrical connection..................................... ImageMOS 20 20 20 21 22 22 22 22 22 24 26 26 26 26 26 26 27 27 27 28 28 31 32 32 35 64 67 69 72 Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 5 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Reference Documentation ImageMOS No Description Digital Camera Reference Design utilizing the MCM20027 Name of Document Roadrunner Application Note Release Date May 4 2001 Contact/Location of Info 1 http://www.motorola.com/adc/imaging http://www.motorola.com/adc/imaging 2 Information on MCM20027 Optics Information on Strobe Timing Optic Application note Strobe Timing Application Note Feb 7 2001 3 May 30 2001 http://www.motorola.com/adc/imaging Table 1. Reference Documentation MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 6 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 1.0 MCM20027 Overview The MCM20027 is a solid state CMOS Active CMOS Imager (ACITM) that integrates the functionality of a complete analog image acquisition, digitizer, and digital signal processing system on a single chip. The image sensor comprises a format pixel array with 1280x1024 active elements. The image size is fully programmable to user defined windows of interest. The pixels are on a 6.0m pitch. High sensitivity and low noise are a characteristic of the pinned "shared diffusion" photodiode architecture utilized in the pixels. Standard microlenses further enhance the sensitivity. The sensor is available with Bayer patterned Color Filter Arrays (CFAs) for color output or as a monochrome imager. Integrated timing and programming controls allow video or still image capture modes.Frame rates are programmable while keeping Master Clock frequency constant. User programmable row and column start/stop allow windowing to a minimum 1x1 pixel window (see "Active Window of Interest Control" on page 12). Windowing can also be performed by subsampling in multiple pixel increments to allow digital zoom (see "Active Window Sub-sampling Control" on page 12). The analog video output of the pixel array is processed by an on chip analog signal processing pipeline. Correlated Double Sampling (see "Correlated Double Sampling (CDS)" on page 15) eliminates the sensor reset noise without the need to capture and subtract a reset frame per live video frame. The Frame Rate Clamp (FRC) enables real time optical black level calibration and offset correction (see "Frame Rate Clamp (FRC)" on page 15). The programmable analog gain consists of exposure or global gain to map the signal swing to the ADC input range, and white balance gain to perform color white balance in the analog domain. The ASP signal chain consists of : (1) Column op-amp(1.5X fixed gain) (2) Column DOVA (1.5X fixed gain) (3) White Balance PGA (0.88-2.82X) (4) Global PGA (0.67X - 5.92X) (5) Global DOVA (2.0X fixed gain) These Digitally Programmable Amplifiers (DPGAs) allow real time color gain correction for Auto White Balance (see "White Balance Control PGA" on page 16) as well as global gain adjustment (see "Exposure Global Gain PGA" on page 16); offset calibration (see "Pro- grammable Per-Column Offset" on page 16 and "Global Digital Offset Voltage Adjust (DOVA)" on page 19) can be done on a per column basis and globally. This percolumn offset correction can be applied by using stored values in the on chip registers. A 10-bit Redundant Signed Digit (RSD) ADC converts the analog data to a 10-bit digital word stream. The fully differential analog signal processing pipeline serves to improve noise immunity, signal to noise ratio, and system dynamic range. The sensor uses an industry standard two line I 2C complaint serial interface. (see page 26). The MCM20027 operates with a single 3.3V power supply ( see "Electrical Characteristics" on page 53) with no additional biases and requires only a single Master Clock for operation upto 13.5MHz. It is housed in a 48 pin ceramic LCC package (see "MCM20027 Packaging Information" on page 69). The MCM20027 is designed taking into consideration interfacing requirements to standard video encoders. In addition to the 10 bit bayer encoded data stream, the sensor outputs the valid frame, line and pixel sync signals needed for encoding. The sensor interfaces with a variety of commercially available video image processors to allow encoding into various standard video formats. The MCM20027 is an elegant and extremely flexible single chip solution that simplifies a system designer's tasks of image sensing, processing, digital conversion, and digital signal processing to a high performance, low cost, low power IC. One that supports among others a wide range of low power, portable consumer digital imaging applications. 2.0 MCM20027 Architecture 2.1 Pixel Architecture The MCM20027 ImageMOSTM (1) sensor comprises of a 1280 x 1024 active pixel array and supports progressive scan mode. The MCM20027 utilizes the Kodak patented "Shared Floating Diffusion" pixel design 3. This design enables two adjacent Row pixels` photodiodes to share the same floating diffusion transistor. (see Figure 2, on page 8). 1. ImageMOS is a Motorola trademark 2. Patents held jointly by Motorola and Kodak 3. Kodak Patent pending Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 7 MOTOROLA SEMICONDUCTOR TECHNICAL DATA The basic operation of the pixel relies on the photoelectric effect where due to its physical properties silicon is able to detect photons of light. The photons generate electron-hole pairs in direct proportion to the intensity and wavelength of the incident illumination. The application of an appropriate bias allows the user to collect the electrons and meter the charge in the form of a useful parameter such as voltage. The pixel architecture also requires all pixels in a row to have common Reset , Transfer 1 and 2, Floating diffu- ImageMOS sion and Row Select gate controls. In addition all pixels have common supply (VDD) and ground (VSS) connections. An optimized cell architecture provides enhancements such as noise reduction, fill factor maximizations, and antiblooming. The use of pinned photodiodes (2) and proprietary transfer gate devices in the photoelements enables enhanced sensitivity in the entire visual spectral range and a lag free operation. RESET GATE SHARED FLOATING DIFFUSION GATE ROW SELECT GATE TRANSFER GATE 1 TRANSFER GATE 2 PHOTODIODE ROW 1 PHOTODIODE ROW2 Figure 2. Shared Floating Diffusion Pixel Architecture TRANSFER GATE 1 Tint TRANSFER GATE 2 Tint RESET GATE ROW SELECT GATE SHARED FLOATING DIFFUSION GATE Trow T=0 T=1 T=2 T=3 Trow T=4 T=5 T=6 How it works? In brief, initially during Integration @T=0, both Transfer Gates 1 and 2 and the Reset Gate is Open (On-Active High). Transfer Gate 1 then Closes (Off) @ T=1, thereby allowing Photodiode 1 to charge its well capacitance. At this time Photodiode 2 is held at Reset level by having Transfer Gate 2 and the Reset Gate open (On). After 1 Row Period [Trow], @T=2 ,Transfer Gate 2 closes (Off). This action causes Photodiode 2 to start charging. When the integration (charging) of Photdiode 1 has MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 8 MOTOROLA SEMICONDUCTOR TECHNICAL DATA neared completion, @ T=3, the Reset Gate closes (Off). The charge off the well capacitance of Photodiode 1 is then transfered to the Shared Floating Diffusion Gate @ T=4 when Transfer Gate 1 opens (On). Also @T=4 the Shared Diffusion gate and the Row Select gate opens (On). This action causes charge from the floating diffusion to be read out as a Voltage value for that pixel on Row 1. @T=5 the Row Select gate and the Floating diffusion close (Off) while the Reset gate opens (On). This is occurs in preparation of readout of Row 2. ImageMOS When the integration (charging) of Photodiode 2 has neared completion, the Reset Gate closes (Off) again. The charge off the Well Capacitance of Photodiode 2 is then transfered to the Shared Floating Diffusion Gate @ T=6 when Transfer Gate 2 opens (On) and then the same readout procedure as before occurs. The nominal photoresponse of the MCM20027 is shown in Figure 3 R G B S R F , 4 0 0 to 1 1 0 0 n m 1 0 .9 0 .8 0 .7 Relative Pixel Response 0 .6 0 .5 0 .4 0 .3 0 .2 0 .1 0 400 - 0 .1 W a v e le n g th , n m R E D P ix e ls G r e e n - B P ix e ls G r e e n - B P ix e ls B lu e P ix e ls 500 600 700 800 900 1000 1100 Figure 3. MCM20027 Nominal spectral response In addition to the imaging pixels, there are additional pixels called dark and dummy pixels at the periphery of the imaging section (see Figure 2). The dark pixels are covered by a light blocking shield rendering the pixels underneath insensitive to photons. These pixels provide the sensor means to measure the dark level offset which is used downstream in the signal processing chain to perform auto black level calibration. The dummy pixels are provided at the array's periphery to eliminate inexact measurements due to light piping into the dark pixels adjacent to active pixels. The output of these pixels should be discarded. Electronic shuttering, also known as electronic exposure timing in photographic terms, is a standard feature. The pixel integration time can be widely varied from a small fraction of a given frame readout time to the entire frame time. 2.2 Color Separation and Fill Factor Enhancement The MCM20027 family is offered with the option of monolithic polymer color filter arrays (CFAs). The combination of an extremely planarized process and propriatary color filter technology result in CFAs with superior spectral and transmission properties. The standard option is a primary (RGB) "Bayer" pattern (see Figure 4), however, facility to produce customized CFAs including complementary (CMYG) mosaics also exists. Applications requiring higher sensitivity can benefit from the optional micro-lens arrays shown in Figure 5. The lenslet arrays can improve the fill factor (aperture ratio) of the sensor by 1.5-2x depending on the F number of the main lens used in the camera system. Microlenses yield greatest benefits when the main lens has a high F number. As a caution, telecentric optical design is a requirement due to the limited optical acceptance angle of the lenslit. The optical acceptance angle is approximately 15 degrees (see figure 5a). Due to the lenslits being placed in the same area/position over all the photodiodes on the sensor, hence, care should be taken when taking into consideration the telecentric design for especially the outermost pixels.The fill factor of the pixels without microlenses is 32%. With Microlens the fill factor improves to approximately 45% to 50%. Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 9 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 3.1 Continuous Frame Rolling Shutter capture (CFRS) [Default] The default mode of image capture is the "Continuous Frame Rolling Shutter" capture mode (CFRS). This mode will yield frame rates up to 10fps at 13.5 MHz MCLK. In this mode the image integration and row readout take place in parallel. While a row of pixels is being read out, another row(s) are being integrated. Readout of each row follows the Integration of that row. Therefore the Integration of the rows are staggered out due to the Readout of sequential rows occurring one after the other (see "Integration Time in CFRS mode:" on page 13). In CFRS, after one frame has completed integrating, the first row of the second frame automatically begins integrating. The readout of the rows also follow the same routine. The waveforms depicting the CFRS output data stream refer to Figure 6, on page 11 and Figure 7, on page 12. 3.1.1 CFRS Video Encoded Data stream The Pixel Data Stream Signal Control Register, (Table 53), on page 62 allows the user to select how the output pixel data stream in Continuous Frame Rolling Shutter mode is encoded/formatted. In default mode, internally generated signals SOF, VCLK, HCLK etc. drive the integration and readout of the pixel data frames but only the valid pixel data is readout of the sensor. When a "1" is written to bit 5 of the Pixel Data Stream Signal Control Register, (Table 53), on page 62, it causes the output pixel data to be encoded with SOF, VCLK and End Of Frame signals. It accomplishes this by attaching the pixel data with certain predefined signal data. The Video Encoded Signal Definitions, (Table 2), on page 10 defines the data that represents the SOF, VCLK and End of Frame signals. Signal SOF Description Start of Row readout (i.e.. Readout of Row 1) Start of Row readout of Rows 2+ Readout of last Row complete Data 3FF3FF3FF3FF G1 B R G2 G1 B R G2 R G1 R BB G2 G1 B B G2 Figure 4. On-chip Bayer CFA A 15o 15o B Iris microlenses Figure 5. a) 15 degrees acceptance angle b)Improvement in pixel sensitivity results from focusing incident light on photo sensitive portions of the pixel by using microlenses 3.0 Frame Capture Modes There exists two frame capture modes: 1) Continuous Frame Rolling Shutter mode (CFRS) 2) Single Frame Rolling Shutter mode (SFRS) The sensor can be put into either one of the aforementioned modes by writing either "1" or "0" to Bit 6 of Capture Mode Control Register, (Table 29), on page 48. VCLK End Of Frame 3FF3FF000000 000000000000 Table 2. Video Encoded Signal Definitions MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 10 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.2 Single Frame Rolling Shutter capture mode (SFRS) This mode of capture refers to non-interlaced or sequential row by row scanning of the entire sensor in a single pass for the purpose of capturing a single frame. The start of Integration in this mode is triggered by the SYNC signal. Similar to the CFRS capture mode, Readout of each row follows the Integration of that row. Therefore the Integration of the rows are staggered out as well due to the Readout of the sequential rows occurring one after the other (see "Integration Time in SFRS ImageMOS mode" on page 14). This process continues until all Rows have been integrated and readout. Once readout of the entire frame is complete, the sensor awaits a new SYNC signal before it starts integration and readout of another frame. The waveforms depicting the SFRS output data stream refer to Figure 8, on page 12 NOTE!! The faster the clock speed , the closer the sequential Integration start times are. Frame Time = 1064 row times Row Time = 1338 MCLKs WOI = 1280 Columns x 1024 Rows starting at row 16, column 8 SOF VCLK HCLK row 1037 row 1038 row 1039 row 1037 row 1038 row 1039 BLANK row 16 row 17 row 18 row 19 row 16 row 17 row 18 Figure 6. CFRS Default Frame Waveform MCLK SOF Row Time = vcwd + 39 105 106 row 17 31 32 14 15 1 2 3 col. 1286 col. 1287 1 2 3 4 5 6 7 8 1 2 3 1 2 3 VCLK HCLK Pixel Array Values row 16 ADC[9:0] Valid Pixel Data Revision 8.0 - 28 November 2001 : MCM20027 col. 8 col. 9 col. 10 row 19 MOTOROLA 11 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Figure 7. CFRS Default Line Waveform ImageMOS SYNC T = (cintd + 1) * Row Time SOF VCLK HCLK row 1037 row 1038 row 1039 row 16 row 17 row 18 row 19 Standard Frame Timing (Figure 18) Figure 8. SFRS Waveform 4.0 Active Window of Interest Control The pixel data to be read out of the device is defined as a `Window of Interest' (WOI). The window of interest can be defined anywhere on the pixel array at any size. The user provides the upper-left pixel location and the size in both row and column depth to define the WOI. The WOI is defined using the WOI Pointer, WOI Depth, and WOI Width registers, (Table 32 on page 51 through Table 39 on page 53). Please refer to Figure 9 for a pictorial representation of the WOI within the active pixel array. 5.0 Active Window Sub-sampling Control The user can further control the size of the Active Window that is read out by sub sampling the already defined Active Window Of Interest (See "Active Window of Interest Control" on page 12). Subsampling enables the pixel data to be readout in 1 pixel or 2 pixel increments depending if you are subsampling in either monochrome (1 pixel) or bayer pixel (2 pixel) space in four different sampling rates in each direction: full, 1/2, 1/4, or 1/8. The user controls the subsampling via the Subsample Control Register, (Table 30), on page 49. An example of Bayer space sub-sampling is shown in Figure 10. 0 0 1295 ACTIVE PIXEL ARRAY WOI Row Depth (wrd) WOI Pointer (wcp,wrp) Window of Interest (WOI) G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G G B G B G B G B G B G B R G R G R G R G R G R G Sub-sample Control Register = x0010101b = Progressive Scan Bayer Pattern Read 1 Pattern, Skip 1 Pattern in both directions Figure 10. Bayer Space Sub-sampling Example WOI Column Width (wcw) 1047 Figure 9. WOI Definition MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 12 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 6.0 Frame Rate and Integration Time Control In addition to the minimum time required to readout the selected resolution and WOI, the user has the ability to control the frame rates while operating in either Continuous Frame Rolling Shutter capture mode (CFRS) and Single Frame Rolling Shutter (SFRS). The frame rate can be defined as the time required to readout an entire frame of data plus the required boundary timing. This is done by varying the size of a number of parameters identified in later sections, the main one being the Virtual Frame surrounding the WOI. Please refer to Figure 11 for a pictorial description of the Virtual Frame and its relationship to the WOI 6.2 Integration Time in CFRS mode: In Continuous Frame Rolling Shutter capture mode, the Integration time is defined as: Integration Time=Tint = (cintd + 1) * Trow where cintd is the number of virtual row times desired for integration time. Therefore, the integration time in CFRS mode can be adjusted in steps of virtual frame row times.The user controls cintd via the Integration Time MSB Register, (Table 40), on page 54 and Integration Time LSB Register, (Table 41), on page 55. Row Time (Trow) is the length of time required to read one row of the virtual frame and can be defined as: Trow = (vcwd + shsd + shrd + 19) * MCLKperiod . 0 0 WOI Row Depth (wrd) WOI Pointer (wcp,wrp) vcw[13:0] where vcwd defines the number of columns in the virtual frame and shsd and shrd are internal timing control registers. The user controls vcwd via the CFRS Virtual Frame Column Width registers (Table 44 on page 56 and Table 45 on page 56). The user controls the shsd and shrd values via the Internal Timing Control Register 1 (shs time definition); Table 50 and Table 51, "Internal Timing Control Register 2 (shr time definition)," on page 60. Window of Interest (WOI) WOI Column Width (wcw) Virtual Frame vrd[13:0] Figure 11. Virtual Frame Definition NOTE!! In Continuous Frame Rolling Shutter (CFRS) capture mode, the Integration time upper limit is bounded by the Frame time (see "CFRS Frame Time/Rate:" on page 13). 6.1 CFRS Frame Time/Rate: In Continuous Frame Rolling Shutter capture mode, the Frame time is completely defined by the size of the Virtual Frame and can be expressed as: Frame Time = Tframe = (vrdd + 1) * Trow where vrdd defines the number of rows in the virtual frame. The user controls vrdd via the Virtual Frame Row Depth registers (Table 42 on page 55 and Table 43 on page 55). Frame Rate = (Frame time)-1 i.e.. Tint < Tframe Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 13 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 6.3 SFRS Frame Time/Rate: In Single Frame Rolling Shutter capture mode the Frame time is defined as: Frame time = Tframe= Integration time+Readout time Readout time is the amount of time to readout the data after integration of the row has been completed. It is defined as follows: Readout time = (vrdd + 1) * Trow where vrdd defines the number of rows in the virtual frame. The user controls vrdd via the CFRS Virtual Frame Row Depth registers (Table 42 on page 55 and Table 43 on page 55). Trow = (vcwd + shsd + shrd + 19) * MCLKperiod For Integration time see "Integration Time in SFRS mode" on page 14 ImageMOS NOTE!! vcwd and cintd are typically varied frame to frame Calculations: Row Time =Trow = (vcwd + shsd + shrd + 19) = (1290 + 10 + 10 + 19) / 13.5e6 = 98.44s Integration Time = (cintd + 1) * Trow =(350+1)*98.44s =34.5ms Readout time = (vrdd + 1) * Trow = Frame time in CFRS mode 6.3.1 Integration Time in SFRS mode The Integration time in Single Frame Rolling Shutter capture mode is the same as in Rolling Shutter Capture Mode. For further information, see "Integration Time in CFRS mode:" on page 13. The only difference is that in this mode the Integration time is NOT bounded by the Frame time Frame Time in CFRS mode = (vrdd + 1) * Trow Tframe =(1034 + 1)* 98.44 = 101.34 ms Frame Time in SFRS mode = Tframe = Integration time+Readout time = 34.5ms + 101.34ms = 135.84ms 6.4 Example of Frame time/rate and Integration Time in CFRS and SFRS modes The following illustrates how to determine the Frame time/ rate and Integration time in both capture modes: Assumptions: 1) Active Window of Interest = 1280 x 1024 i.e.. (wcwd)=1279 (wrdd)=1023 2) Virtual Column Width (vcwd)= 1290 3) Virtual Row Depth (vrdd) = 1034 4) Sample & hold time (shsd) = 10 5) Sample & hold time (shrd) = 10 6) Integration Time (cintd)= 350 7) MCLK = 13.5 Mhz Results Capture Mode CFRS SFRS Tint 34.5ms 34.5ms Tframe 101.34 ms 135.84ms NOTE!! CFRS Integration time = 34.5ms because: Tint < Tframe = (vrdd + 1) * Trow (see "Integration Time in CFRS mode:" on page 13) MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 14 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 7.0 Analog Signal Processing Chain Overview The MCM20027's analog signal processing (ASP) chain incorporates Correlated Double Sampling (CDS), Frame Rate Clamp (FRC), two Digitally Programmable Gain Amplifiers (DPGA), Offset Correction (DOVA), and a 10-bit Analog to Digital Converter (ADC). To see a pictorial depiction of this chain refer to "Specifications" on page 2 7.1 Correlated Double Sampling (CDS) The uncertainty associated with the reset action of a capacitive node results in a reset noise which is equal to kTC; C being the capacitance of the node, T the temperature and k the Boltzmann constant. A common way of eliminating this noise source in all image sensors is to use Correlated Double Sampling. The output signal is sampled twice, once for its reset (reference) level and once for the actual video signal. These values are sampled and held while a difference amplifier subtracts the reference level from the signal output. Double sampling of the signal eliminates correlated noise sources (see ."Conceptual block diagram of CDS implementation." on page 15) CDSP1 S/H1 V+ AVIN CDSP2 S/H2 AMP V- ImageMOS begins a new frame. The MCM20027 uses optical black (dark) pixels to aid in establishing this reference. CapLRCA 0.1f LRCLMP 1X Previous LRCLMP BUF + FRC CLRCA Vcm LRCLMP Vcm Stage 1X LRCLMP LRCLMP + BUF - + Diff Amp - V+ VLRCLMP Vcm CLRCB CapLRCB 0.1f Figure 13. FRC Conceptual Block Diagram On the MCM20027, dark pixel input signals should be sampled for a minimum of 137s to allow the two 0.1F capacitors at the CLRCA and CLRCB pins sufficient time to charge for 10-bit accuracy. This guarantees that the FRC's "droop" will be maintained at <750 V, thus assuring the specified ADC 10-bit accuracy at +0.5 LSB. Therefore, at maximum operational frequency (13.5 MHz), the imager would require a number of frames to establish the dark pixel reference for subsequent active pixel processing. The dark pixel sample period is automatically controlled internally and it is set to skip the first 3 dark rows and then sample the next 2 dark rows. When "dark clamping" is active, each dark pixel is processed and held to establish pixel reference level at the CLRCA and CLRCB pins. During this period, the FRC's differential outputs (V+ and V- on the Diff Amp, Figure 13) are clamped to Vcm. Together, these actions help to eliminate the dark level offset, simultaneously establishing the desired zero code at the ADC output. Care should be exercised in choosing the capacitors for the CLRCA, B pins to reflect different frame rates. The user can disable this function via the FRC Definition Register; Table 54 and the Power Configuration Register, (Table 19), on page 41 (Check this - should be referring o FRC clamp ON/OFF) which will allow the ASP chain to drift in offset Per-Column Digital Offset Voltage Adjust (DOVA), and controls the number of rows to clamp on. Figure 12. Conceptual block diagram of CDS implementation. 7.2 Frame Rate Clamp (FRC) The FRC (Figure 13) is designed to provide a feed forward dark level subtract reference level measurement. In the automatic FRC mode, the optical black level reference is re-established each time the image sensor Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 15 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 7.3 Programmable Per-Column Offset A programmable per-column offset adjustment is available on the MCM20027. In order to reduce the risk and have the ability to cover any mode of repetitive column Fixed Pattern Noise (FPN), there exists 64 registers that can be programmed with a DC offset that is added to all columns. (Mod64 Column Offset registers; Table 27). Each register is 6 bits, (5 bits plus 1 sign bit), providing+/ - 32 register values. The DC register values is added to each of the 64 columns registers to provide the total offset value. This set of 64 values is then repeatedly applied to each bank of 64 in the sensor via the column DOVA stage of the ASP chain. The Column DOVA DC Register; Table 26, is used to set the initial offset of the pixel output in a range that will facilitate per-column offset data generation for varying operational conditions. In most operational scenarios, this register can be left in its default state of 00h. This is a pre-image processing gain in comparison to the Global DOVA Register (see section )which is a post image processing chain gain (pre A2D gain) 7.4 Digitally Programmable Gain Amplifiers (DPGA) for White Balance and Exposure Gain Two DPGAs are available in the analog signal processing chain. These are used to perform white balance and exposure gain functions. 7.4.1 White Balance Control PGA The sensor produces three primary color outputs, Red, Green and Blue. These are monochrome signals that represent luminance values in each of the primary colors. When added in equal amounts they mix to make neutral color. White balancing is a technique where the gain coefficients of the green(0), red, blue, and green(3) pixels comprising the Bayer pattern (see Figure 14.) are set so as to equalize their outputs for neutral color scenes. Since the sensitivity of the two green pixels in the Bayer pattern may not be equal, an individual color gain register is provided for each component of the Bayer pattern. Once all color gain registers are loaded with the desired gain coefficients ,according to which gain mode (see "Gain Modes" on page 17) has been set, white balance is then achieved in real time and in analog space. These gain coefficient values are then selected and applied to the pixel output via a high speed path, the delay of which is much shorter than the pixel clock rate. Real time updates can be performed to any of the gain registers. However, latency associated with the I2C interface should be taken into consideration before changes occur. In most applications, users will be able to assign predefined settings such as daylight, fluorescent, tungMOTOROLA ImageMOS sten, and halogen to cover a wide gamut of illumination conditions. Both DPGA designs use switched capacitors to minimize accumulated offset and improve measurement accuracy and dynamic range. The white balance gain registers are 6-bits and can be programmed to allow gain of 0.696x to 2.74x in varying steps. The user programs the individual gain coefficients into the MCM20027 via the Color Gain Registers (Table 8 through Table 11). For the default Bayer configuration of the color filter array; Figure 4, the Color Gain Register addresses are as follows: Reg (00h): green pixel of a green-red row; Reg (01h): red pixel; Reg (02h): blue pixel; and Reg (03h): green pixel of a blue-green row. The MCM20027 is presently available with only a Bayer CFA, however, it is designed to support other novel color configurations. This is accomplished via the Color Tile Configuration Register, (Table 12), on page 37 and the Color Tile Row Definition registers (Table 13 through Table 16). Green (0) Red (1) Blue (2) Green (3) 6 6 6 6 6 DPGA 0.7x-27x G(0) B(2) R(1) G(3) Figure 14. Color Gain Register Selection 7.4.2 Exposure Global Gain PGA The global gain DPGA provides a 0.67x to 7.5x (approx) programmable gain adjustment for dynamic range. The gain of the amplifier is linearly programmable using a six bit gain coefficients on 2 6-bit PGA gain registers in varying steps depending on which exposure gain mode it is set at i.e. RAW or LIN or LIN2 (PGA Gain Mode, (Table 25), on page 45). The user programs the global gain via the Exposure PGA Global Gain Register A, (Table 23), on page 44. Revision 8.0 - 28 November 2001 : MCM20027 16 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 7.4.3 Gain Modes There exists different gain modes that are available when the sensor is performing White Balance and Exposure gain. The Gain mode utilized for White balance and Exposure gain can be selected by the user writing different values to the register described in Table 25, "PGA Gain Mode," on page 45. Register No 00h ImageMOS There are two different Gain modes for White Balance and there are three different Gain modes for the Exposure gain refer to White Balance Gain modes and Gain Formulas; Table 3 and Exposure Gain modes and Gain Formulas; Table 4 for more info. Register Name DPGA Color 1 Gain Register; Table 8 Variable cg1 Gain Modes RAW Gain Steps 0-32 33-63 Gain Formula 0.6956 + (0.02174* cg1d) 1.391+ (0.0434* (cg1d-32) 0.6956 +(0.0434 x cg1d) 0.6956 + (0.02174* cg2d) 1.391+ (0.0434* (cg2d-32) 0.6956 +(0.0434 x cg2d) 0.6956 + (0.02174* cg3d) 1.391+ (0.0434* (cg3d-32) 0.6956 +(0.0434 x cg3d) 0.6956 + (0.02174* cg4d) 1.391+ (0.0434* (cg4d-32) 0.6956 +(0.0434 x cg4d) Gain Range 0.69-1.39 1.39-2.74 0.69-2.74 0.69-1.39 1.39-2.74 0.69-2.74 0.69-1.39 1.39-2.74 0.69-2.74 0.69-1.39 1.39-2.74 0.69-2.74 LINEAR 01h DPGA Color 2 Gain Register; Table 9 cg2 RAW 0-47 0-32 33-63 LINEAR 02h DPGA Color 3 Gain Register; Table 10 cg3 RAW 0-47 0-32 33-63 LINEAR 03h DPGA Color 4 Gain Register; Table 11 cg4 RAW 0-47 0-32 33-63 LINEAR 0-47 Table 3. White Balance Gain modes and Gain Formulas Green-Red Pixel Data Red Pixel Data DPGA Color 1 Gain Register DPGA Color 2 Gain Register Blue Pixel Data Green-Blue Pixel Data DPGA Color 3 Gain Register DPGA Color 4 Gain Register NOTE!! The Diagrams above illustrates how the Color Gain Registers apply the gain onto each individual color pixel data: Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 17 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Register No 10h Register Name Exposure PGA Global Gain Register A; Table 23 Variable gg1 Gain Modes RAW Gain Steps 0-32 33-63 Gain Formula 0.6956 + (0.02174* gg1d) 1.391+ (0.0434* (gg1d-32) 0.6956 +(0.0434 x gg1d) 0.6956 + (0.0434 * gg2d) 0.6956 + (0.02174* cg2d) 1.391+ (0.0434* (cg2d-32) 0.6956 +(0.0434 x cg2d) 0.6956 + (0.0434 * gg2d) Gain Range 0.69-1.39 1.39-2.74 0.69-2.74 0.69-3.60 0.69-1.39 1.39-2.74 0.69-2.74 0.69-3.60 LINEAR LINEAR 2 21h Exposure PGA Global Gain Register B; Table 24 gg2 RAW 0-47 0-67 0-32 33-63 LINEAR LINEAR 2 0-47 0-67 Table 4. Exposure Gain modes and Gain Formulas The Diagram below illustrates how the Exposure Gain Registers apply the gain onto the pixel data: Pixel Data Exposure PGA Gain Register A Exposure PGA Gain Register B MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 18 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 7.5 Global Digital Offset Voltage Adjust (DOVA) A programmable global offset adjustment is available on the MCM20027. A user defined offset value is loaded via a 6-bit signed magnitude programming code via the Global DOVA Register, (Table 28), on page 47. Offset correction allows fine-tuning of the signal to remove any additional residual error which may have accumulated in the analog signal path. This function is performed directly before analog to digital conversion and introduces a fixed gain of 2.0X. This feature is useful in applications that need to insert a desired offset to adjust for a known system noise floor relative to AVSS and offsets of amplifiers in the analog chain. ImageMOS 7.6 Analog to Digital Converter (ADC) The ADC is a fully differential, low power circuit. A pipelined, Redundant Signed Digit (RSD) algorithmic technique is used to yield an ADC with superior characteristics for imaging applications. Integral Noise Linearity (INL) and Differential Noise Linearity (DNL) performance is specified at +1.0 and +0.5, respectively, with no missing codes. The input voltage resolution is 2.44 mV with a full-scale 2.5 V pp input (2.5 Vpp/210). The input dynamic range of the ADC is programmed via a Programmable Voltage Reference Generator. The positive reference voltage (VREFP) and negative reference voltages (VREFM) can be programmed from 2.5V to 1.25V and 0V to 1.25V respectively in steps of 5mV via the Reference Voltage Registers (Table 17 and Table 18). This feature is used independently or in conjunction with the DPGAs to maximize the system dynamic range based on incident illumination. The default input range for the ADC is 1.9V for VREFP and 0.6V for VREFM hence allowing a 10 bit digitization of a 1.3V peak to peak signal. Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 19 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8.0 Sensor External Controls (Additional Operational Conditions) The MCM20027 includes initialization, standby modes, and external reference voltage outputs to afford the user additional applications flexibility. ImageMOS 8.3 Tristate Mode The sensors HCLK, SOF, VCLK, SYNC and STROBE output signals as well as the pixel output data can be tristated via the Tristate Control Register, (Table 21), on page 42. 8.1 Initialization The INIT input pin (#42) controls reinitialization of the MCM20027. This serves to assure controlled chip and system startup. Control is asserted via a logic high input. (i.e.. Asserting a Logic high "1" initializes all the Registers, while asserting a Logic low "0" returns the sensor to normal operation). This state must be held a minimum of 1 ms and a 1 ms "wait period" should be allowed before chip processing to ensure that the start-up routines within the MCM20027 have run to completion, and to guarantee that all holding and bypass capacitors, etc. have achieved their required steady state values. Tasks which are accomplished during startup include: reset of the utility programming registers and initialization to their default values (please refer to previous section for settings), reset of all internal counters and latches, and setup of the analog signal processing chain. Another method of saving power consumption is to applying an active high signal to the INIT pin (#42) but Note - Doing this will also cause initialization of the chip . 8.4 References CVREFP, CVREFM The MCM20027 contains all internally generated references and biases on-chip for system simplification. An internally generated differential bandgap regulator derives all the ADC and other analog signal processing required references. The user should connect 0.1F capacitors to the CVREFP and CVREFM pins (#15 and #14 respectively) to accurately hold the biases. 8.5 Common Mode References: VAG, VAGREF and VAGRETURN The MCM20027 holds the Common Mode Reference Voltages on the chip to a stable value. In order to achieve this stable value, the VAG (pin #16), VAGREF(pin #18 ) and VAGRETURN (pin #17) have to be connected to two 0.1F capacitors in the manner described in the diagram below: VAG (pin #16) 8.2 Standby Mode The standby mode option is implemented to allow the user to reduce system power consumption during periods which do not require operation of the MCM20027. This feature allows the user to extend battery life in low power applications. By utilizing this mode, the user may reduce dynamic power consumption from 250mW RMS nominal @13.5MHz to <100 uW in the standby mode. The standby mode is activated by writing a "1" to bit 0 of "Power Configuration Register" on page 41. Writing a "0" restores normal operation. 0.1F VAGRETURN (pin #17) 0.1F VAGREF (pin #18) MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 20 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8.6 Internal Bias Current Control The ASP chain has internally generated bias currents that result in an operating power consumption of nearly 400mW approx. (Accurate value will be given upon sensor testing). By attaching a resistor between pin 20, EXTRES; and Pin19, the user can reduce the power consumption of the device. This feature is enabled by writing a 1b to bit res of the Power Configuration Register. Additional power savings can be achieved at lower clock rates. Note - The External Bias resistor Input pin (EXTRESP - pin #20) should be connected to the ETRESRTN (pin#19) in the manner described in the diagram below. ImageMOS EXTRESP (pin #20) Resistor EXTRESRTN (pin #19) Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 21 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9.0 Sensor Output/Input Signals 9.1 Start Of Data Capture (SYNC) This signal is utilized by the sensor to indicate the start of integration (data capture) in Single Frame Rolling Shutter capture mode (SFRS). For more info refer to Figure 15, on page 22, Figure 8, on page 12 and Figure 16, on page 24. This signal can be generated internally by the sensor or be driven via Pin # 46 of the sensor (see Figure 20, on page 67). To set whether the signal is generated internally or externally, as well as other settings to this signal, refer to Sync and Strobe Control register, (Table 31), on page 50. 9.2 Start Of Row Readout (SOF) This signal triggers/indicates the start of Row Readout of the frame. This signal is an Output and can be read via Pin # 48 of the sensor (see Figure 20, on page 67). The SOF signal delay as well as its length can be set by the user via SOF Delay Register, (Table 46), on page 57 and SOF & VCLK Signal Length Control Register, (Table 48), on page 57. For timing diagrams depicting the use of the SOF signal refer to Figure 15, on page 22, Figure 6, on page 11, Figure 7, on page 12 ,Figure 8, on page 12 and Figure 16, on page 24. ImageMOS 9.3 Horizontal Data SYNC (VCLK) This signal triggers the Readout of the sequential rows of the frame. This signal is an Output and can be read via Pin # 44 of the sensor (see Figure 20, on page 67). The VCLK signal delay in relation to SOF, as well as its length can be set by the user via VCLK Delay Register, (Table 47), on page 57 and SOF & VCLK Signal Length Control Register, (Table 48), on page 57. For timing diagrams depicting the use of the VCLK signal refer toFigure 15, on page 22, Figure 6, on page 11, Figure 7, on page 12 ,Figure 8, on page 12 and Figure 16, on page 24. 9.4 Data Valid (HCLK) This signal triggers/indicates a single active pixel data has been readout (eg Column 5 of Row 10 data has been read out). This signal is an Output and can be read via Pin # 45 of the sensor (see Figure 20, on page 67). The HCLK signal delay can be set by the user via HCLK Delay Register, (Table 52), on page 60. For timing diagrams depicting the use of the HCLK signal refer to Figure 15, on page 22, Figure 6, on page 11, Figure 7, on page 12 ,and Figure 8, on page 12. MCLK tsusync SYNC thsync tdsof SOF tdvclk VCLK tdfhclk tdrhclk HCLK tdadc ADC[9:0] Figure 15. Pixel Data Bus Iinterface Timing Specifications (see Table Below) MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 22 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS PIXEL DATA BUS INTERFACE TIMING SPECIFICATIONS (see Figure 15) Symbol fmax thsync tsusync tdsof tdvclk tdrhclk tdfhclk tdadc tstrobe MCLK maximum frequency SYNC hold time w.r.t MCLK SYNC setup time w.r.t MCLK MCLK to SOF delay time MCLK to VCLK delay time Rising edge of MCLK to rising edge of HCLK delay time Falling edge of MCLK to falling edge of HCLK delay time MCLK to ADC[9:0] delay time MCLK to STROBE delay time Characteristic Min 1 3.5 3.0 8 8.5 7.5 3 8 8 Typ 11.5 13 13.5 13 5 13 13 Max 13.5 9 8.5 21.5 22 22 10.5 21.5 21.5 Unit MHz ns ns ns ns ns ns ns ns Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 23 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 9.5 Strobe Signal The Strobe signal is a output pin on the MCM20027 sensor that can be used to activate `Flash/Strobe illumination modules". It can be activated by writing a "1" to bit 3 of "Sync and Strobe Control register" on page 50 while in SFRS mode. When activated, the Strobe signal goes high (Active) when all Rows are Integrating simultaneously, and ends one Row period (Trow) before the ImageMOS last Row begins to Integrate. (see 3"Frame Rate and Integration Time Control" on page 13). The start of the strobe signal can also be set by the user. In default mode, when the strobe is activated, the signal fires 2 Row Periods (Trow) before the first Row begins to Readout and last for a length of 1 Trow .A sample timing diagram for the Strobe signal can be seen in Figure 16, on page 24: Tframe SYNC 1st ROW OF INTEGRATION Tint 2nd ROW OF INTEGRATION Tint 3rd ROW OF INTEGRATION Tint LAST ROW OF INTEGRATION Tint SOF VCLK STROBE Trow Trow Trow TrowTrow Trow Trow Trow Tstrobe2 Tstrobe1 Figure 16. Strobe Timing Diagram in SFRS capture mode MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 24 MOTOROLA SEMICONDUCTOR TECHNICAL DATA To ensure that Strobe signal fires, the integration time must be large enough to ensure that all rows are integrating simulanteously for at least 2 Row periods (Trow) (see "Frame Rate and Integration Time Control" on page 13) where Trow = (vcwd + shsd + shrd + 19) To accomplish this - ensure that the Integration time (cintd) greater than 2 Row periods (Trow) larger than the active Window of Interest Row depth. Min. Integration time =Tintmin=(cintmin+1)*Trow cintmin=wrdd+x ImageMOS Variables: Integration Time (cintmin) is the main variable used to control the time of the Strobe signals. Tintmin=(cintmin+1)*Trow Calculations: Row Time =Trow = (vcwd + shsd + shrd + 19) = (1290 + 10 + 10 + 19) / 13.5e6 = 98.44s Tintmin=(cintmin+1)*Trow cintmin=wrdd+x where x > 2 where wrdd is the Window Of Interest Row depth. Tstrobe1= Trow Tstrobe2= Tintmin- (wrdd+1)*Trow where x > 2 Let cintmin= wrdd+x where x > 2 where x=4 = 1023 + 4 = 1029 Therefore, Tintmin= 101.39 Tstrobe1= 98.44s EXAMPLE: Below you will find an example of how to ensure that the strobe signal will fire and to determine the length of the STROBE signal in default mode: (Refer to Figure 16, on page 24 for timing analysis) Goal (For example purpose): Strobe Signal that lasts for at least 250us, which is the length of a typical strobe/flash event. Results: Tstrobe2= Tintmin- (wrdd+2)*Trow = 3 * Trow = 295us Signal Assumptions: 1) Active Window of Interest = 1280 x 1024 Value 98us 101ms 98us 295us 202ms Trow Tint Tstrobe1 Tstrobe2 Tframe ie. (wcwd)=1279 (wrdd)=1023 2) Virtual Column Width (vcwd)= 1290 3) Virtual Row Depth (vrdd) = 1034 4) Sample & hold time (shsd) = 10 5) Sample & hold time (shrd) = 10 6) MCLK = 13 Mhz NOTE!! Refer to Figure 16, on page 24 for timing analysis Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 25 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 10.0 I2C Serial Interface The I2C is an industry standard which is also compatible with the Motorola bus (called M-Bus) that is available on many microprocessor products. The I2C contains a serial two-wire half-duplex interface that features bidirectional operation, master or slave modes, and multimaster environment support. The clock frequency on the system is governed by the slowest device on the board. The SDATA and SCLK are the bidirectional data and clock pins, respectively. These pins are open drain and will require a pull-up resistor to VDD of 1.5 k to 10 k (see page 66). The I2C is used to write the required user system data into the Program Control Registers in the MCM20027. The I2C bus can also read the data in the Program Control Register for verification or test considerations. The MCM20027 is a slave only device that supports a maximum clock rate (SCLK) of 100 kHz while reading or writing only one register address per I2C start/stop cycle. The following sections will be limited to the methods for writing and reading data into the MCM20027 register. For a complete reference to I 2C, see "The I 2C Bus from Theory to Practice" by Dominique Paret and CarllFenger, published by John Wiley & Sons, ISBN 0471962686. 10.1 MCM20027 I2C Bus Protocol The MCM20027 uses the I2C bus to write or read one register byte per start/stop I2C cycle as shown in Figure 17 and Figure 18. These figures will be used to describe the various parts of the I2C protocol communications as it applies to the MCM20027. MCM20027 I2C bus communication is basically composed of following parts: START signal, MCM20027 slave address (0110011b) transmission followed by a R/ W bit, an acknowledgment signal from the slave, 8 bit data transfer followed by another acknowledgment signal, STOP signal, Repeated START signal, and clock synchronization. 10.2 START Signal When the bus is free, i.e. no master device is engaging the bus (both SCLK and SDATA lines are at logical "1"), a master may initiate communication by sending a START signal. As shown in Figure 17, a START signal is defined as a high-to-low transition of SDATA while SCLK is high. This signal denotes the beginning of a new data transfer and wakes up all the slaves on the bus. 10.3 Slave Address Transmission MOTOROLA ImageMOS The first byte of a data transfer, immediately after the START signal, is the slave address transmitted by the master. This is a 7-bit calling address followed by a R/ W bit. The seven-bit address for the MCM20027, starting with the MSB (AD7) is 0110011b. The transmitted calling address on the SDATA line may only be changed while SCLK is low as shown in Figure 17. The data on the SDATA line is valid on the High to Low signal transition on the SCLK line. The R/W bit following the 7-bit tells the slave the desired direction of data transfer: * * 1 = Read transfer, the slave transitions to a slave transmitter and sends the data to the master 0 = Write transfer, the master transmits data to the slave 10.4 Acknowledgment Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDATA line low at the 9th clock (see Figure 17). If a transmitted slave address is acknowledged, successful slave addressing is said to have been achieved. No two slaves in the system may have the same address. The MCM20027 is configured to be a slave only. 10.5 Data Transfer Once successful slave addressing is achieved, data transfer can proceed between the master and the selected slave in a direction specified by the R/W bit sent by the calling master. Note that for the first byte after a start signal (in Figure 17 and Figure 18), the R/W bit is always a "0" designating a write transfer. This is required since the next data transfer will contain the register address to be read or written. All transfers that come after a calling address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCLK is low and must be held stable while SCLK is high as shown in Figure 17. There is one clock pulse on SCLK for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the SDATA low at the ninth clock. So one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDATA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling. Revision 8.0 - 28 November 2001 : MCM20027 26 MOTOROLA SEMICONDUCTOR TECHNICAL DATA If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDATA line for the master to generate STOP or START signal. 10.6 Stop Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called a Repeated START. A STOP signal is defined as a low-to-high transition of SDATA while SCLK is at logical "1" (see Figure 17). The master can generate a STOP even if the slave has generated an acknowledge bit at which point the slave must release the bus. MSB SCLK 1 2 3 4 5 6 LSB 7 8 9 MSB 1 2 3 4 5 6 7 ImageMOS 10.7 Repeated START Signal A Repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. As shown in Figure 18, a Repeated START signal is being used during the read cycle and to redirect the data transfer from a write cycle (master transmits the register address to the slave) to a read cycle (slave transmits the data from the designated register to the slave). LSB 8 9 SDATA AD7 AD6 AD5 AD4 AD3 AD2 AD1 "0" "1" "1" "0" "0" "1" "1" MCM20027 I 2C Bus Address D7 D6 D5 D4 D3 D2 D1 D0 Start Signal MCM20027 Register Address Write Ack Bit from MCM20027 LSB Ack Bit from MCM20027 MSB SCLK 1 2 3 4 5 6 7 8 9 SDATA D7 D6 D5 D4 D3 D2 D1 D0 Data to write MCM20027 Register Ack Stop Bit Signal from MCM20027 Figure 17. WRITE Cycle using I2C Bus 10.8 I2C Bus Clocking and Synchronization Open drain outputs are used on the SCLK outputs of all master and slave devices so that the clock can be synchronized and stretched using wire-AND logic. This means that the slowest device will keep the bus from going faster than it is capable of receiving or transmitting data. After the master has driven SCLK from High to Low, all the slaves drive SCLK Low for the required period that is needed by each slave device and then releases the SCLK bus. If the slave SCLK Low period is greater than the master SCLK Low period, the resulting SCLK bus signal Low period is stretched. Therefore, synchronized clocking occurs since the SCLK is held low by the device with the longest Low period. Also, this method can be used by the slaves to slow down the bit rate of a transfer. The master controls the length of time that the SCLK line is in the High state. The data on the SDATline is valid when the master switches the SCLK line from a High to a Low. Slave devices may hold the SCLK low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCLK line. Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 27 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 10.9 Register Write Writing the MCM20027 registers is accomplished with the following I2C transactions (see Figure 17): * * Master transmits a START Master transmits the MCM20027 Slave Calling Address with "WRITE" indicated (BYTE=66h, 102d, 01100110b) MCM20027 slave sends acknowledgment by forcing the SDATA Low during the 9th clock, if the Calling Address was received Master transmits the MCM20027 Register Address MCM20027 slave sends acknowledgment by forcing the SDATA Low during the 9th clock after receiving the Register Address Master transmits the data to be written into the register at the previously received Register Address MCM20027 slave sends acknowledgment by forcing the SDATA Low during the 9th clock after receiving the data to be written into the Register Address Master transmits STOP to end the write cycle * * ously received from the master; MCM20027 transitions to slave-receiver Master does not send an acknowledgment (NAK) Master transmits STOP to end the read cycle * * * * * * 10.10 Register Read Reading the MCM20027 registers is accomplished with the following I2C transactions (see Figure 18): * * Master transmits a START Master transmits the MCM20027 Slave Calling Address with "WRITE" indicated (BYTE=66h, 102d, 01100110b) MCM20027 slave sends acknowledgment by forcing the SData Low during the 9th clock, if the Calling Address was received Master transmits the MCM20027 Register Address MCM20027 slave sends acknowledgment by forcing the SData Low during the 9th clock after receiving the Register Address Master transmits a Repeated START Master transmits the MCM20027 Slave Calling Address with "READ" indicated (BYTE = 67h, 103d, 01100111b) MCM20027 slave sends acknowledgment by forcing the SDATA Low during the 9th clock, if the Calling Address was received At this point, the MCM20027 transitions from a "Slave-Receiver" to a "Slave-Transmitter" MCM20027 sends the SCLK and the Register Data contained in the Register Address that was previ- * * * * * * * * MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 28 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS SCLK 1 MSB 2 3 4 5 6 7 LSB 8 9 1 MSB D7 2 3 4 5 6 7 8 LSB 9 SDATA AD7 AD6 AD5 AD4 AD3 AD2 AD1 "0" "1" "1" "0" "0" "1" "1" MCM20027 I2C Bus Address D6 D5 D4 D3 D2 D1 D0 XX Start Signal MCM20027 Register Address Write Ack Bit from MCM20014 Ack Repeated Bit Start from Signal MCM20027 SCLK 1 MSB 2 3 4 5 6 7 LSB 8 9 At this point the MCM20027 transitions from a "SLAVE-receiver" to a "SLAVE- transmitter" SDATA AD7 AD6 AD5 AD4 AD3 AD2 AD1 "0" "1" "1" "0" "0" "1" "1" MCM20027 I2C Bus Address Read Ack Bit fromMCM20027 SCLK 1 MSB 2 3 4 5 6 7 8 LSB 9 The MCM20027 transitions from a "SLAVE-transmitter" to a "SLAVE-receiver" after the register data is sent SDATA D7 D6 D5 D4 D3 D2 D1 D0 Data from MCM20027 Register No Ack. Bit from MASTER terminates the transfer Stop Signal from MASTER Single Byte Transfer to Master Figure 18. READ Cycle using I2C Bus Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 29 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS I2C SERIAL INTERFACE6 TIMING SPECIFICATIONS (see Figure 19) Symbol fmax M1 M2 M3 M4 M5 M6 M7 M8 M9 CI Cbus Rp 62 7 Characteristic SCLK maximum frequency Start condition SCLK hold time SCLK low period SCLK/SDATA rise time [from VIL = (0.2)*VDD to VIH = (.8)*VDD] SDATA hold time SCLK/SDATA fall time (from Vh = 2.4V to Vl = 0.5V) SCLK high period SDATA setup time Start / Repeated Start condition SCLK setup time Stop condition SCLK setup time Capacitive for each I/O pin Capacitive bus load for SCLK and SDATA Pull-up Resistor on SCLK and SDATA Min 50 4 8 4 4 4 4 4 1.5 Max 400 .3 .3 10 200 10 Unit KHz TMCLK7 TMCLK s8 TMCLK7 s8 TMCLK TMCLK7 TMCLK TMCLK pF pF k9 I C is a proprietary Phillips interface bus The unit TMCLK is the period of the input master clock; The frequency of MCLK is assumed 13.5 MHz 8 The capacitive load is 200 pF 9 A pull-up resistor to VDD is required on each of the SCLK and SDATA lines; for a maximum bus capacitive load of 200 pf, the minimum value of Rp should be selected in order to meet specifications M2 M6 M5 SCLK M1 M8 M4 M7 M8 VIH VIL M3 M9 SDATA Figure 19. I2C SERIAL INTERFACE6 TIMING SPECIFICATIONS MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 30 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 11.0 Suggested Software Register Programming Reference There are number of registers whose default values we have been changed to make the sensor operational with a Digital Still Camera. The registers, there suggested new values (changes) and reason for there change are detailed in Suggested Register Default Value Changes, (Table 5), on page 31 Register No 0Ch Default Values 00h ImageMOS NOTE!! These are only suggested value changes. Depending on the application, there might exist more or less registers whose default values require modifications. Register Name Power Configuration Register; Table 19 New Values 08h Comment Switching External Resistor On for Lower active power consumption White Balance switched from Raw to Linear gain mode . Exposure Gain switched from Raw to Linear 2 gain mode Negative Offset for Analog Signal Processing chain Necessary for switch to SFRS capture mode in addition to Capture Mode Control Register new SOF = 64 MCLKs new VCLK = 8 MCLKs new shs=64 MCLKs increase sample time to sweep all available charge from pixel new shr=64 MCLKs increased reset timesweep all available charge from pixel 22h PGA Gain Mode; Table 25 00h 06h 23h 42h 56h Global DOVA Register; Table 28 Sync and Strobe Control register; Table 31 SOF & VCLK Signal Length Control Register; Table 48 Internal Timing Control Register 1 (shs time definition); Table 50 Internal Timing Control Register 2 (shr time definition); Table 51 00h 02h 0Eh 27h 00h 09h 5Fh 0Ah 00h 60h 0Ah 00h Table 5. Suggested Register Default Value Changes Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 31 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 12.0 MCM20027 Utility Programming Registers 12.1 Register Reference Map The I2C addressing is broken up into groups of 16 and assigned to a specific digital block. The designated block is responsible for driving the internal control bus, when the assigned range of addresses are present on the internal address bus. The grouping designation and assigned range are listed in Table 6. Each block contains registers which are loaded and read by the digital and analog blocks to provide configuration control via the I2C serial interface. Table 7 contains all the I2C address assignments. The table includes a column indicating whether the register values are shadowed with respect to the sensor interHex Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Address Range 00h - 2Fh 40h - 7Fh 80h - BFh Block Name Analog Register Interface Sensor Interface Column Offset coeff. Table 6. I2C Address Range Assignments face. If the register is shadowed, the sensor interface will only be updated upon frame boundaries, thereby eliminating intraframe artifacts resulting from register changes. Register Function DPGA Color 1 Gain Register (Green of Green-Red Row) DPGA Color 2 Gain Register (Red) DPGA Color 3 Gain Register (Blue) DPGA Color 4 Gain Register (Green of Blue-Green Row) Unused Color Tile Configuration Register Color Tile Row 1 Definition Register Color Tile Row 2 Definition Register Color Tile Row 3 Definition Register Color Tile Row 4 Definition Register Negative Voltage Reference Code Register Positive Voltage Reference Code Register Power Configuration Register Factory Use Only Reset Control Register Device Identification (read only) Defa ult 0Eh 0Eh 0Eh 0Eh Ref. Table Table 8, page 35 Table 9, page 35 Table 10, page 36 Table 11, page 36 Shadow ed? Yes Yes Yes Yes 05h 44h EEh 00h 00h 76h 80h 00h FUO 00h 50h Table 12, page 37 Table 13, page 38 Table 14, page 38 Table 15, page 39 Table 16, page 39 Table 17, page 40 Table 18, page 40 Table 19, page 41 FUO Table 20, page 42 No No No No No No No No FUO No No Table 7. I2C Address Assignments MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 32 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex Address 10h 11h 12h 13h 14-1F 20h 21h 22h 23h 24 - 3Fh 40h 41h 42h 43h - 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h Defa ult 0Eh ImageMOS Register Function Exposure PGA Global Gain Register A Unused Tristate Control Register; Table 21 Programable Bias Generator Control register Unused Column DOVA DC Register Exposure PGA Global Gain Register B PGA Gain Mode Global DOVA Register Unused Capture Mode Control Register Sub-sample Control Register Sync and Strobe Control register Unused WOI Row Pointer MSB Register WOI Row Pointer LSB Register WOI Row Depth MSB Register WOI Row Depth LSB Register WOI Column Pointer MSB Register WOI Column Pointer LSB Register WOI Column Width MSB Register WOI Column Width LSB Register Factory Use Only Integration Time MSB Register Integration Time LSB Register Virtual Frame Row Depth MSB Register Virtual Frame Row Depth LSB Register Ref. Table Table 23, page 44 Shadow ed? Yes 03h 00h Table 21, page 42 Table 22, page 43 00h 0Eh 00h 00h Table 26, page 46 Table 24, page 45 Table 25, page 45 Table 28, page 47 No Yes No No 2Ah 10h 02h Table 29, page 48 Table 30, page 49 Table 31, page 50 Yes Yes Yes 00h 10h 03h FFh 00h 08h 04h FFh Table 32, page 51 Table 33, page 51 Table 34, page 51 Table 35, page 52 Table 36, page 52 Table 37, page 53 Table 38, page 53 Table 39, page 53 Yes Yes Yes Yes Yes Yes Yes Yes 04h FFh 04h 27h Table 40, page 54 Table 41, page 55 Table 42, page 55 Table 43, page 55 Yes Yes Yes Yes Table 7. I2C Address Assignments (Continued) Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 33 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex Address 52h 53h 54h 55h 56h 57h 58h - 5Eh 5Fh 60h 61h-63h 64h 65h 66h 67h 68h 69h - 7Fh 80-BF C0h -FF h Defa ult 05h 13h 4Ch 02h 0Eh 04h ImageMOS Register Function Virtual Frame Column Width MSB Register Virtual Frame Column Width LSB Register SOF Delay Register VCLK Delay Register SOF & VCLK Signal Length Control Register Greycode and Readout Control Register Unused Internal Timing Control Register 1 (shs time definition) Internal Timing Control Register 2 (shr time definition) Factory Use Only HCLK Delay Register Pixel Data Stream Signal Control Register Factory Use Only FRC Definition Register Factory Use Only Unused Mod64 Column Offset registers Unused Ref. Table Table 44, page 56 Table 45, page 56 Table 46, page 57 Table 47, page 57 Table 47, page 57 Table 49, page 58 Shadow ed? Yes Yes No No No No 0Ah 0Ah Table 50, page 59 Table 51, page 60 Yes Yes 5Ch 00h Table 52, page 60 Table 53, page 62 Yes 24h Table 54, page 63 00h Table 27, page 47 Table 7. I2C Address Assignments (Continued) MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 34 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 13.0 Detailed Register Block Assignments This section describes in further detail the functional operation of the various MCM20027 programmable registers. The registers are subdivided into various blocks for ease of addressability and use (see Table 6). In each table where a suffix code is used; h = hex, b = binary, and d = decimal. 13.1 Analog Register Interface Block The address range for this block is 00h to BFh. ImageMOS The four Color Gain Registers, Color Tile Configuration Register, and four Color Tile Row definitions define how white balance is achieved on the device. Six-bit gain codes can be selected for four separate colors: Table 8, Table 9, Table 10, and Table 11. Gain for each individual color register is programmable given the gain function defined in the table. The gain function used depends on what Gain mode (White balance gain mode) the sensor is set (PGA Gain Mode; Table 25).The user programs these registers to account for changing light conditions to assure a white balanced output. The default value in each register is provides for a unity gain. In addition, the default CFA pattern color is listed in the title of each register. Default 0Eh 2 1 lsb (0) 13.1.1 Analog Color Configuration Address 00h msb (7) 6 5 DPGA Color 1 Gain Code Green of Green-Red Row 4 3 x Bit Number 7-6 5-0 x Function Unused Gain cg1[5] cg1[4] cg1[3] Description cg1[2] cg1[1] cg1[0] Reset State xx 001110b Unused PGA Gain Mode Raw Gain Mode [cg1d= 0-32d] ---> Gain = 0.6956 + (0.02174* cg1d) Raw Gain Mode [cg1d= 33-63d] --> Gain = 1.391+ (0.0434* (cg1d-32) (Range 0.696 - 2.736) Linear Gain Mode -----> Gain = 0.6956 +(0.0434 x cg1d) (Range 0.696 - 2.736) Table 8. DPGA Color 1 Gain Register Address 01h msb (7) 6 5 DPGA Color 2 Gain Code Red 4 3 2 1 Default 0Eh lsb (0) x Bit Number 7-6 x Function Unused cg2[5] cg2[4] cg2[3] Description cg2[2] cg2[1] cg2[0] Reset State xx Unused Table 9. DPGA Color 2 Gain Register Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 35 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Address 01h msb (7) 6 5 ImageMOS DPGA Color 2 Gain Code Red 4 3 2 1 Default 0Eh lsb (0) x 5-0 x Gain cg2[5] cg2[4] cg2[3] cg2[2] cg2[1] cg2[0] 001110b PGA Gain Mode Raw Gain Mode [cg2d= 0-32d] ---> Gain = 0.6956 + (0.02174* cg2d) Raw Gain Mode [cg2d= 33-63d] --> Gain = 1.391+ (0.0434* (cg2d-32) (Range 0.696 - 2.736) Linear Gain Mode -----> Gain = 0.6956 +(0.0434 x cg2d) (Range 0.696 - 2.736) Table 9. DPGA Color 2 Gain Register Address 02h msb (7) 6 5 DPGA Color 3 Gain Code Blue 4 3 2 1 Default 0Eh lsb (0) x Bit Number 7-6 5-0 x Function Unused Gain cg3[5] cg3[4] cg3[3] Description cg3[2] cg3[1] cg3[0] Reset State xx 001110b Unused PGA Gain Mode Raw Gain Mode [cg3d= 0-32d] ---> Gain = 0.6956 + (0.02174* cg3d) Raw Gain Mode [cg3d= 33-63d] --> Gain = 1.391+ (0.0434* (cg3d-32) (Range 0.696 - 2.736) Linear Gain Mode -----> Gain = 0.6956 +(0.0434 x cg3d) (Range 0.696 - 2.736) Table 10. DPGA Color 3 Gain Register Address 03h msb (7) 6 5 DPGA Color 4 Gain Code Green of Blue-Green Row 4 3 2 1 Default 0Eh lsb (0) x Bit Number 7-6 x Function Unused cg4[5] cg4[4] cg4[3] Description cg4[2] cg4[1] cg4[0] Reset State xx Unused Table 11. DPGA Color 4 Gain Register MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 36 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Address 03h msb (7) 6 5 ImageMOS DPGA Color 4 Gain Code Green of Blue-Green Row 4 3 2 1 Default 0Eh lsb (0) x 5-0 x Gain cg4[5] cg4[4] cg4[3] cg4[2] cg4[1] cg4[0] 001110b PGA Gain Mode Raw Gain Mode [cg4d= 0-32d] ---> Gain = 0.6956 + (0.02174* cg4d) Raw Gain Mode [cg4d= 33-63d] --> Gain = 1.391+ (0.0434* (cg4d-32) (Range 0.696 - 2.736) Linear Gain Mode -----> Gain = 0.6956 +(0.0434 x cg4d) (Range 0.696 - 2.736) Table 11. DPGA Color 4 Gain Register The Color Tile Configuration Register; Table 12, defines the maximum number of lines and the maximum number of colors per line. A maximum of four row and four column definitions are permitted. The Color Tile Configuration Register defaults to two lines and two colors per Address 05h msb (7) 6 5 line. The user should leave this register in default unless a unique CFA option has been ordered. This register can be configured to any pattern combination of 1, 2, or 4 rows and 1, 2, or 4 columns. Default 05h 2 1 lsb (0) Color Tile Configuration 4 3 x Bit Number 7-4 3-2 x Function Unused Columns x x nc[1] Description nc[0] nr[1] nr[0] Reset State xxxx 01b Unused 00b = 1 Column in tile. 01b = 2 Columns in tile. 1xb = 4 Columns in tile. 00b = 1 Row in tile. 01b = 2 Rows in tile. 1xb = 4 Rows in tile. Table 12. Color Tile Configuration Register 1-0 Rows 01b The Color Tile Row Definition registers; Table 13, Table 14, Table 15, and Table 16 define the sequence of colors for each respective line. Each byte wide line definition allows a maximum of four unique color definitions using 2 bits per color in a given line. Gain programming for each color was described earlier in this section. The default line definitions are colors 00b, 01b, 00b, 01b for row 1 and 10b, 11b, 10b, 11b for row 2 which supports a Bayer pattern as defined in section 2.2. The user should leave these registers in default unless a unique CFA option has been ordered. For the default Bayer configuration of the color filter array; Figure 4, the Color Gain Register addresses are as follows: Reg (01h): green pixel of a green-red row; Reg (00h): red pixel; Reg (03h): blue pixel; and Reg (02h):green pixel of a blue-green row. The predefined Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 37 MOTOROLA SEMICONDUCTOR TECHNICAL DATA gain values programmed in the respective registers are applied to pixel outputs as they are being read. Address 06h msb (7) 6 5 ImageMOS Color Tile Row 1 Definition Green - Red Row 4 3 2 1 Default 44h lsb (0) r1c4[1] Bit Number 7-6 5-4 3-2 1-0 r1c4[0] Function Color 4 Color 3 Color 2 Color 1 r1c3[1] r1c3[0] r1c2[1] Description r1c2[0] r1c1[1] r1c1[0] Reset State 01b 00b 01b 00b Fourth Color in Row 1(Green) Third Color in Row 1 (Red) Second Color in Row 1 (Green) First Color in Row 1 (Red) Table 13. Color Tile Row 1 Definition Register Address 07h msb (7) 6 5 Color Tile Row 2 Definition Blue - Green Row 4 3 2 1 Default EEh lsb (0) r2c4[1] Bit Number 7-6 5-4 3-2 1-0 r2c4[0] Function Color 4 Color 3 Color 2 Color 1 r2c3[1] r2c3[0] r2c2[1] Description r2c2[0] r2c1[1] r2c1[0] Reset State 11b 10b 11b 10b Fourth Color in Row 2 (Blue) Third Color in Row 2 (Green) Second Color in Row 2 (Blue) First Color in Row 2 (Green) Table 14. Color Tile Row 2 Definition Register MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 38 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 08h msb (7) 6 5 Color Tile Row 3 Definition Unused 4 3 2 1 Default 00h lsb (0) r3c4[1] Bit Number 7-6 5-4 3-2 1-0 r3c4[0] Function Color 4 Color 3 Color 2 Color 1 r3c3[1] r3c3[0] r3c2[1] Description r3c2[0] r3c1[1] r3c1[0] Reset State 00b 00b 00b 00b Fourth Color in Row 3 Third Color in Row 3 Second Color in Row 3 First Color in Row 3 Table 15. Color Tile Row 3 Definition Register Address 09h msb (7) 6 5 Color Tile Row 4 Definition Unused 4 3 2 1 Default 00h lsb (0) r4c4[1] Bit Number 7-6 5-4 3-2 1-0 r4c4[0] Function Color 4 Color 3 Color 2 Color 1 r4c3[1] r4c3[0] r4c2[1] Description r4c2[0] r4c1[1] r4c1[0] Reset State 00b 00b 00b 00b Fourth Color in Row 4 Third Color in Row 4 Second Color in Row 4 First Color in Row 4 Table 16. Color Tile Row 4 Definition Register 13.1.2 Reference Voltage Adjust Registers The analog register block allows programming the input voltage range of the analog to digital converter to match the saturation voltage of the pixel array. The voltage reference generator can be programmed via two registers; nrv (0 to 1.25V) Table 17, prv (2.5V to 1.25V) Table 18, in 5mV steps. A 00h value in the prv register represents a reference output voltage of 2.5V. A 00h value in the nrv register represents output voltage of 0V. The default settings for the two registers produce a 1.9V reference on prv and 0.6V on nrv outputs. When adjusting Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 39 MOTOROLA SEMICONDUCTOR TECHNICAL DATA these values, the user should keep the voltage range centered around 1.25V. Address 0Ah msb (7) 6 5 ImageMOS Voltage Reference "Negative" Code 4 3 2 1 Default 76h lsb (0) nrv[7] Bit Number 7-0 nrv[6] Function Reference nrv[5] nrv[4] nrv[3] Description nrv[2] nrv[1] nrv[0] Reset State 01110110b (0.6V) Voltage = 0.0 + (5mV * nrcd) Table 17. Negative Voltage Reference Code Register Address 0Bh msb (7) 6 5 Voltage Reference "Positive" Code 4 3 2 1 Default 80h lsb (0) prv[7] Bit Number 7-0 prv[6] Function Reference prv[5] prv[4] prv[3] Description prv[2] prv[1] prv[0] Reset State 10000000b (1.9V) Voltage = 2.5 - (5mV * prvd) Table 18. Positive Voltage Reference Code Register 13.1.3 Analog Control Registers The Analog Register Block also contains a Power Configuration Register; Table 19, and a Reset Control Register; Table 20. The Power Configuration Register controls the internal analog functionality that directly effect power consumption of the device. An external precision resistor pin is available on the MCM20027 that may be used to more accurately regulate the internal current sources. This serves to minimize variations in power consumption that are caused by variations in internal resistor values as well as offer a method to reduce the power consumption of the device. The default for this control uses the internally provided resistor which is nominally 12.5k. This feature is enabled by setting the res bit of the Power Configuration Register and placing a resistor between the pin; EXTRES, and ground. Figure 11 depicts the power savings that can be achieved with an external re- sistor at a specific clock rate. Power is further reduced at lower clock rates. The pbg bit of the Power Configuration Register; Table 19, is used to enable/disable the "Programmable Bias Generator". When this bit is enabled, the user can vary the power consumption of the White Balance PGA (PGAWB), Exposure gain PGA A (PGAEXPa), Exposure gain PGA B (PGEXPb), Frame Rate Clamp (FRC), Column Offset DOVA (COL_DOVA), Global offset DOVA (DOVE) and/or the Analog to Digital converter (A2D) between half an full current (power) consumption. in the Programable Bias Generator Control register; Table 22. When this bit is disabled, it will use the power configured by the internal or external resistor (bit 3). MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 40 MOTOROLA SEMICONDUCTOR TECHNICAL DATA The MCM20027 is put into a standby mode via the I2C interface by setting the sby bit of the Power Configuration Register. Address 0Ch msb (7) 6 5 ImageMOS Power Configuration 4 3 2 1 Default 00h lsb (0) x Bit Number 7-5 4 x Function Unused Prog Bias Gen Int/Ext Resistor Select Software Clamp Software Clamp Software Standby x pbg res Description ssc sc sby Reset State x 0 Unused 0b = Prog Bias Gen Disabled 1b = Prog Bias Gen Enabled 0b = Internal Resistor 1b = External Resistor 0b = Select internal Clamp 1b = Select software Clamp 0b = Clamp Off 1b = Clamp On (if ssc = 1) 0b = Soft Standby inactive 1b = Soft Standby active Table 19. Power Configuration Register 3 0b 0b 2 1 0b 0b 0 Additional control of the MCM20027 can be had using the Reset Control Register; Reset Control Register; Table 20. Setting the sir bit of this register will reset all the non programmable Sensor interface registers to a known reset state. Setting the par bit of this register will reset all the Sensors non programmable Post ADC registers to a known reset state. Setting the asp bit of this register will reset all the sensors registers in the ASP processing chain to a known reset state. Setting the ssr bit of this register will reset all the nonuser programmable registers to a known reset state. This is useful in situations when control of the MCM20027 has been lost due to system interrupts and the device needs only to be restarted using the earlier user programmed values. Setting the sit bit allows the user to completely reset the MCM20027 to the default state via the serial control Interface. For both reset bits, ssr and sit, the user must return those bits to 0 to enable continued operation Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 41 MOTOROLA SEMICONDUCTOR TECHNICAL DATA . Address 0Eh msb (7) 6 5 ImageMOS Reset Control 4 3 2 1 Default 00h lsb (0) x Bit Number 7-5 4 x Function Unused ASP (A2D) Reset Post ADC Reset Sensor Interface Reset State Reset Soft Reset x asr par Description sir ssr sit Reset State xxx 0b 0b 0b Unused 0b = Normal Mode 1b = Reset registers in the A2D to 0 0b = Normal Mode 1b = Reset non-programmable Post ADC Registers to Reset state. 0b = Normal Mode 1b = Reset non-programmable Sensor Interface resgisters to Reset state. 0b = Normal Mode 1b = Reset all non-programmable registers to the Reset state 0b = Normal Mode 1b = Reset all registers. (Same functions as setting the INIT pin) Table 20. Reset Control Register 3 2 1 0b 0b 0 The Tristate Control Register; Table 21 is used to set signals into Tristate mode. When the tsctl bit is reset (i.e.. "0") the HCLK, SOF, VCLK, SYNC and STROBE output signals are set to Tristate mode. When the tspix Address 12h msb (7) 6 5 bit is reset (i.e. "0") the pixel output data is set to Tristate mode. Tristate Control B 4 3 2 1 Default 03h lsb (0) FUO Bit Number 7-3 1 FUO Function FUO tsctl FUO FUO FUO Description FUO tsctl tspix Reset State 000000b 1b Factory Use Only 0 - Outputs in Tristate 1 - Outputs driving Table 21. Tristate Control Register MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 42 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Address 12h msb (7) 6 5 ImageMOS Tristate Control B 4 3 2 1 Default 03h lsb (0) FUO 0 FUO tspix FUO FUO FUO FUO tsctl tspix 1b 0 - Outputs in Tristate 1 - Outputs driving Table 21. Tristate Control Register The Programable Bias Generator Control register; Table 22 can be used by the user to vary the power consumption of the White Balance PGA (PGAWB), Exposure gain PGA A (PGAEXPa), Exposure gain PGA B (PGEXPb), Frame Rate Clamp (FRC), Column Offset DOVA (COL_DOVA), Global offset DOVA (DOVE) and/ or the Analog to Digital converter (A2D) between half an full current (power) consumption. Address 13h msb (7) 6 5 In order for this Register to be used, the pbg bit of the Power Configuration Register; Table 19 has to be enabled. Programable Bias Generator Control 4 3 2 1 Default 00h lsb (0) x Bit Number 7 6 adp Function Unused A to D Converter (A2D) Global Dova PGA Exp. Gain B PGA Exp. Gain A PGA White Balance Col_Dova gdp egb ega Description wbp cdp fcp Reset State xb 0b Unused 1b = Full Current (Power) consumption [80/100] 0b = Half Current (Power) consumption [40/50] 1b = Full Current (Power) consumption [80/100] 0b = Half Current (Power) consumption [40/50] 1b = Full Current (Power) consumption [80/100] 0b = Half Current (Power) consumption [40/50] 1b = Full Current (Power) consumption [80/100] 0b = Half Current (Power) consumption [40/50] 1b = Full Current (Power) consumption [80/100] 0b = Half Current (Power) consumption [40/50] 1b = Full Current (Power) consumption [80/100] 0b = Half Current (Power) consumption [40/50] Table 22. Programable Bias Generator Control register 5 0b 0b 0b 0b 0b 4 3 2 1 Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 43 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Address 13h msb (7) 6 5 ImageMOS Programable Bias Generator Control 4 3 2 1 Default 00h lsb (0) x 0 adp Frame Rate Clamp gdp egb ega wbp cdp fcp 0b 1b = Full Current (Power) consumption [80/100] 0b = Half Current (Power) consumption [40/50] Table 22. Programable Bias Generator Control register 13.2 Gain Calibration Block The Exposure PGA Global Gain Register A; Table 23 and the Exposure PGA Global Gain Register B; Table 24, allows the user to set a global gain via two 6 bit register which are applied universally to all the pixel outputs. This enables the user to account for varying light conditions.The Gain range depends on what the Exposure Gain Mode (PGA Gain Mode; Table 25)is set. If Address 10h msb (7) 6 5 The Exposure gain mode is set at either Raw or Linear, then Exposure PGA Global Gain Register A; Table 23 and Exposure PGA Global Gain Register B; Table 24 are both utilized. But if it is set at Linear 2 gain mode, then only Exposure PGA Global Gain Register A; Table 23 is used. ( Default 0Eh 2 1 lsb (0) Exposure PGA Global Gain A 4 3 x Bit Number 7-6 5-0 x Function Unused Gain gg1[5] gg1[4] gg1[3] Description gg1[2] gg1[1] gg1[0] Reset State xx 001110 Unused PGA Gain Mode Raw Gain Mode [gg1d= 0-32d] ---> Gain = 0.6956 + (0.02174* gg1d) Raw Gain Mode [gg1d= 33-63d] --> Gain = 1.391+ (0.0434* (gg1d32) (Range 0.696 - 2.736) Linear Gain Mode -----> Gain = 0.6956 + (0.0434 * gg1d) (Range 0.696 - 2.736) Linear 2 Gain Mode ----> Gain = 0.484 +(0.12 x gg1d) (Range 0.484 - 7.488) Table 23. Exposure PGA Global Gain Register A MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 44 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 21h msb (7) 6 5 Exposure PGA Global Gain B 4 3 2 1 Default 0Eh lsb (0) x Bit Number 7-6 5-0 x Function Unused Gain gg2[5] gg2[4] gg2[3] Description gg2[2] gg2[1] gg2[0] Reset State xxb 001110 Unused PGA Gain Mode Raw Gain Mode [gg2d= 0-32d] ---> Gain = 0.6956 + (0.02174* gg2d) Raw Gain Mode [gg2d= 33-63d] --> Gain = 1.391+ (0.0434* (gg2d32) (Range 0.696 - 2.736) Linear Gain Mode -----> Gain = 0.6956 + (0.0434 * gg2d) (Range 0.696 - 2.736) Table 24. Exposure PGA Global Gain Register B The PGA Gain Mode; Table 25, is the register where the PGA Gain modes for the White Balance and Exposure gains can be selected. There are two different Gain modes for White Balance and there are three different Gain modes for the Exposure gain. White Balance Gain modes: 1) Raw gain mode - 32 steps @ 0.02174/step - 32 steps @ 0.04340/step 2) Linear gain mode - 48 steps @ 0.04340/step Exposure Gain Modes: 1) Raw gain mode - 32 steps @ 0.02174/step - 32 steps @ 0.04340/step i.e. PGA Global Gain A Register= Raw gain mode PGA Global Gain B Register= Raw gain mode 2) Linear gain mode - 48 steps @ 0.04340/step i.e. PGA Global Gain A Register= Linear gain mode PGAGlobal Gain B Register= Linear gain mode 3) Linear 2 gain mode - 64 steps @ ~ 0.12/step i.e. PGA Global Gain A Register= Linear 2 gain mode PGA Global Gain B Register= Not used The wbm bit sets the White Balance mode. While the egm[d] bit sets the Exposure gain mode Address 22h msb (7) 6 5 PGA Gain Mode 4 3 2 1 Default 00h lsb (0) x Bit Number x Function x x x Description wbm egm[1] egm[0] Reset State Table 25. PGA Gain Mode Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 45 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Address 22h msb (7) 6 5 ImageMOS PGA Gain Mode 4 3 2 1 Default 00h lsb (0) x 7-3 2 x Unused White Balance Gain Mode Exposure Gain Mode x Unused x x wbm egm[1] egm[0] xxxx 0b 0b = Raw gain mode 1b = Linear gain mode 00b = Raw gain mode 01b = Linear gain mode 1xb = Linear 2 gain mode Table 25. PGA Gain Mode 1-0 00b 13.3 Offset Calibration Block Offset adjustments for the MCM20027 are done in separate sections of the ASP to facilitate FPN removal and final image black level set. The Column DOVA DC Register; Table 26, is used to set the initial offset of the pixel output in a range that will facilitate per-column offset data generation for varying operational conditions. In most operational scenarios, Address 20h msb (7) 6 5 this register can be left in its default state of 00h. This is a pre-image processing gain in comparison to the Global DOVA Register which is a post image processing chain gain (pre A2D gain). This register can also be used to apply a global offset adjust. In this case, the user must take into account the Color Gain and Global Gain registers to determine the resulting offset at the output. Default 00h 2 1 lsb (0) Column DOVA DC 4 3 x Bit Number 7-6 5 x Function Unused Sign cdd[5] cdd[4] cdd[3] Description cdd[2] cdd[1] cdd[0] Reset State xx 0b 00000b Unused 0b = Positive Offset 1b = Negative Offset Offset = 2.6 * cddd (64 steps @ 2.6mV /Step) Table 26. Column DOVA DC Register 4-0 Column DC Offset The Mod64 Column Offset registers; Table 27 are used in conjunction with the Column DOVA DC Register; Table 26 to reduce/eliminate fixed pattern noise (FPN). There are 64 registers that can be programmed with individual offset values. They will be applied to all the columns on a single image frame on a Modular 64 basis.i.e. Register 80h Column offset will be applied to Column 0 , Register 81h Column offset will be applied to Column 1, Register BFh Column offset will be applied to Column 63, Register 80h Column offset will be applied to Column 0..etc.. MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 46 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 80-BFh msb (7) 6 5 Mod64 Column Offset 4 3 2 1 Default 00h lsb (0) x Bit Number 7-6 5 x Function Unused Sign mdd[5] mdd[4] mdd[3] Description mdd[2] mdd[1] mdd[0] Reset State xx 0b 00000b Unused 0b = Positive Offset 1b = Negative Offset Offset = 2.6 * mddd (64 steps @ 2.6mV /Step) 4-0 Mod 64 Column DC Offset Table 27. Mod64 Column Offset registers The Global DOVA Register; Table 28 performs a final offset adjustment in analog space prior to the ADC. The 6-bit register uses its MSB to indicate positive or negative offset. Each bit value changes the offset value by 4 Address 23h msb (7) 6 5 LSB code levels hence giving an offset range of +/-124 LSB. As an example, to program an offset of +92 LSB, the binary representation of +23d i.e. 010111b should be loaded. Default 00h 2 1 lsb (0) Global DOVA 4 3 x Bit Number 7-6 5 x Function Unused Sign gd[5] gd[4] gd[3] Description gd[2] gd[1] gd[0] Reset State xx 0b 00000b Unused 0b = Positive Offset 1b = Negative Offset Offset = 12 * gdd (64 steps @ 12mV /Step) Table 28. Global DOVA Register 4-0 Offset 13.4 Sensor Interface Block 13.4.1 Sensor Output Control The sensor output control registers define how the window of interest is captured and what data is output from the MCM20027. The Capture Mode Control Register; Table 29, defines how the data is captured and how the data is to be provided at the output.. Setting the cms bit will stop the current output data stream at the end of the current frame. Unsetting this bit (cms = 0b) will resume the output of the frame stream. The MCM20027 is in CFRS in default. The user may use this bit to capture data in the CFRS mode and/or SFRS while using the SYNC pin. The SYNC pin triggers a single frame of data to be output from the device in the Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 47 MOTOROLA SEMICONDUCTOR TECHNICAL DATA SFRS mode. Please refer to Figure 14, on page 20 for a timing diagram of this mode. The sp bit is used to define whether SOF is active high or low. SOF is active high in default. The ve bit is used to determine whether VCLK is output at the beginning of all the rows including virtual frame rows or for the WOI rows only. The default is WOI only. The vp bit is used to define whether VCLK is active high or low. VCLK is active high in default. Address 40h msb (7) 6 5 ImageMOS The he bit is used to determine whether HCLK is output continuously or for the WOI pixels only. The default is WOI only. The hp bit is used to define whether HCLK is active high or low. HCLK is active high in default. The hm bit is used to define HCLK is toggled or whetherwhether it is continuously output. Capture Mode Control 4 3 2 1 Default 2Ah lsb (0) FUO Bit Number 7 6 cms Function FUO Capture Mode SOF Phase VCLK Enable VCLK Phase HCLK Enable HCLK Phase HCLK Mode sp ve vp Description he hp hm Reset State 0b 0b 1b 0b 1b 0b 1b 0b Factory Use Only 0b = Continuos Frame Rolling Shutter 1b = Single Frame Rolling Shutter 1b = SOF active high 0b = SOF active low 1b = All virtual frame rows 0b = Window of Interest rows only 1b = Active high 0b = Active low 1b = Continuous 0b = Window of Interest Pixels only 1b = Active high 0b = Active low 1b = Continuous - envelope 0b = Toggles - like MCLK Table 29. Capture Mode Control Register 5 4 3 2 1 0 The Sub-sample Control Register; Table 30, is used to define what pixels of the WOI are read and the method they are read. Using the cm bit, the user can sample the pixel array in either monochrome or Bayer pattern color space. This means that when sampling the rows or columns, the set of pixels read will be gathered as individual pixels MOTOROLA (monochrome) or in color tiles of pixels (Bayer pattern). The pixels will be read in monochrome mode in default. The row sub sampling rate is defined by rf[1:0] while the column sub sampling rate is defined by cf[1:0]. The pixel array is fully sampled in default. Revision 8.0 - 28 November 2001 : MCM20027 48 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 41h msb (7) 6 5 Sub-sample Control 4 3 2 1 Default 10h lsb (0) x Bit Number 7 6-5 4 FUO Function Unused FUO Color Mode Row Frequency FUO cm rf[1] Description rf[0] cf[1] cf[0] Reset State x FUO 1b 00b Unused Factory Use Only 1b = Bayer Pattern Sampling 0b = Monochrome Pattern Sampling 11b = read one row pattern, skip 7 (1/8 sampled) 10b = read one row pattern, skip 3 (1/4 sampled) 01b = read one row pattern, skip one (1/2 sampled) 00b = full sampling 11b = read one column pattern, skip 7 (1/8 sampled) 10b = read one column pattern, skip 3 (1/4 sampled) 01b = read one column pattern, skip one (1/2 sampled) 00b = full sampling Table 30. Sub-sample Control Register 3-2 1-0 Column Frequency 00b The Sync and Strobe Control register; Table 31 is used to control the sync and strobe signals. The sr bit when enabled causes the SYNC signal to go high for exactly one clock cycle, and then returns to a low. It remains low until the sr bit is enabled again. The sa bit when enabled causes the SYNC signal high until this bit is disabled. This causes continuous frame processing. The se bit when enabled will allow for an external signal to drive the SYNC signal via the SYNC pin on the chip. The sae bit when enabled will enable the STROBE signal to be generated automatically by the sensor.This will only work in SFRS (Single Frame Rolling Shutter). The STROBE signal is goes high when all the Rows in the Frame are integrating together. The saw bit allows the user to select how long the STROBE signal is going to be on. If the bit is set to 1 (Setting 1), causes the STROBE Signal to be on from the time all the Rows are integrating to 1 Row time (TROW) before Read-Out of the first Row commences. If Revision 8.0 - 28 November 2001 : MCM20027 the bit is set to 0 (Setting 0), causes the STROBE signal to on for a duration of 1 Row time (TROW) from the time all Rows are integrating The sso bit ,when enabled, forces the STROBE signal and thereby the STROBE Pin high until it is reset back to 0. When this bit is set high - the sae and saw bit settings become negligible. NOTE! Please refer to Figure 15, on page 14 for Strobe Signal timing diagram. MOTOROLA 49 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 42h msb (7) 6 5 SYNC and STROBE Control 4 3 2 1 Default 02h lsb (0) x Bit Number 7-6 5 x Function Unused Strobe Enable Strobe Auto Width Definition Strobe Auto Enabled Exernal SYNC Enabled SYNC Always sso saw sae Description se sa sr Reset State xx 0b 0b Unused 1b = Strobe On 0b = Disabled 1b = Maximum time (Entire time during which all active rows are inte grating) 0b = 1 line 1b = Enabled during integration 0b = Disabled 1b = Enabled 0b = Disabled 1b = Enabled 0b = Disabled 1b = Enabled (Self clearing - will always read "0") 0b = Disabled Table 31. Sync and Strobe Control register 4 3 0b 2 0b 1 1b 0 SYNC Request 0b 13.4.2 Programmable "Window of Interest" The WOI is defined by a set of registers that indicate the upper-left starting point for the window and another set of registers that define the size of the window. Please refer to Figure 9, on page 12 for a pictorial representation of the WOI within the active pixel array. The WOI Row Pointer; wrp[10:0] (Table 32 and Table 33), and the WOI Column Pointer; wcp[10:0] (Table 36 and Table 37), mark the upper-left starting point for the WOI. The WOI Row Pointer; wrp[10:0], has a range of 0d to 1047d whereas the WOI Column Pointer; wcp[10:0] has a usable range of 0d to 1295d. The pointer can be placed anywhere within the active pixel array. The WOI Row Depth; wrd[10:0] (Table 32 and Table 33), and the WOI Column Depth; wcd[10:0] (Table 36 and Table 37), indicate the size of the WOI. The WOI Row Depth; wrd[10:0], has a range of 0d to 1047d whereas the WOI Column Depth; wcd[10:0], has a range of 0d to 1295d. The user should be careful to create a WOI that contains active pixels only. There is no logic in the sensor MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 50 MOTOROLA SEMICONDUCTOR TECHNICAL DATA interface to prevent the user from defining an WOI that addresses non-existent pixels. Address 45h msb (7) 6 5 ImageMOS WOI Row Pointer MSB 4 3 2 1 Default 00h lsb (0) x Bit Number 7-3 2-0 x Function Unused WOI Row Pointer x x x Description wrp[10] wrp[9] wrp[8] Reset State xxxxx 000b Unused In conjunction with the WOI Row Pointer LSB Register (Table 33), forms the 11-bit WOI Row Pointer wrp[10:0] Table 32. WOI Row Pointer MSB Register Address 46h msb (7) 6 5 WOI Row Pointer LSB 4 3 2 1 Default 10h lsb (0) wrp[7] Bit Number 7-0 wrp[6] Function WOI Row Pointer wrp[5] wrp[4] wrp[3] Description wrp[2] wrp[1] wrp[0] Reset State 00010000b (row 16) In conjunction with the WOI Row Pointer MSB Register (Table 32), forms the 11-bit WOI Row Pointer wrp[10:0] Table 33. WOI Row Pointer LSB Register Address 47h msb (7) 6 5 WOI Row Depth MSB 4 3 2 1 Default 03h lsb (0) x Bit Number 7-3 x Function Unused x x x Description wrd[10] wrd[9] wrd[8] Reset State xxxxx Unused Table 34. WOI Row Depth MSB Register Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA 51 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 47h msb (7) 6 5 WOI Row Depth MSB 4 3 2 1 Default 03h lsb (0) x 2-0 x WOI Row Depth x x x wrd[10] wrd[9] wrd[8] 011b In conjunction with the WOI Row Depth LSB Register (Table 35), forms the 11-bit WOI Row Depth wrd[10:0]. Table 34. WOI Row Depth MSB Register Address 48h msb (7) 6 5 WOI Row Depth LSB 4 3 2 1 Default FFh lsb (0) wrd[7] Bit Number 7-0 wrd[6] Function WOI Row Pointer wrd[5] wrd[4] wrd[3] Description wrd[2] wrd[1] wrd[0] Reset State 11111111b (1024 rows) In conjunction with the WOI Row Depth MSB Register (Table 34), forms the 11-bit WOI Row Depth wrd[10:0]. Desired = wrdd + 1. Table 35. WOI Row Depth LSB Register Address 49h msb (7) 6 5 WOI Column Pointer MSB 4 3 2 1 Default 00h lsb (0) x Bit Number 7-3 2-0 x Function Unused WOI Col. Pointer x x x Description wcp[10] wcp[9] wcp[8] Reset State xxxxx 000b Unused In conjunction with the WOI Column Pointer LSB Register (Table 37), forms the 11-bit WOI Column Pointer wcp[10:0] Table 36. WOI Column Pointer MSB Register MOTOROLA Revision 8.0 - 28 November 2001 : MCM20027 52 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 4Ah msb (7) 6 5 WOI Column Pointer LSB 4 3 2 1 Default 08h lsb (0) wcp[7] Bit Number 7-0 wcp[6] Function WOI Col. Pointer wcp5] wcp[4] wcp[3] Description wcp[2] wcp[1] wcp[0] Reset State 00001000b (col. 8) In conjunction with the WOI Column Pointer MSB Register (Table 36), forms the 11-bit WOI Column Pointer wcp[10:0] Table 37. WOI Column Pointer LSB Register Address 4Bh msb (7) 6 5 WOI Column Width MSB 4 3 2 1 Default 04h lsb (0) x Bit Number 7-3 2-0 x Function Unused WOI Col. Width x x x Description wcw[10] wcw[9] wcw[8] Reset State xxxxx 100b Unused In conjunction with the WOI Column Width LSB Register (Table 39), forms the 11-bit WOI Column Width wcw[10:0]. Table 38. WOI Column Width MSB Register Address 4Ch msb (7) 6 5 WOI Column Width LSB 4 3 2 1 Default FFh lsb (0) wcw[7] Bit Number 7-0 wcw[6] Function WOI Row Pointer wcw[5] wcw[4] wcw[3] Description wcw[2] wcw[1] wcw[0] Reset State 11111111b (1280 col.) In conjunction with the WOI Column Width MSB Register (Table 38), forms the 11-bit WOI Column Width wcw[10:0]. Desired = wcwd + 1. Table 39. WOI Column Width LSB Register (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 53 MOTOROLA SEMICONDUCTOR TECHNICAL DATA 13.4.3 Integration Time Control The Integration Time registers; Table 41, Table 40, and Table 41, control the integration time for the pixel array. Integration time for CFRS and SFRS; cint[13:0], is measured in Virtual Row times. Please refer to Figure 11 for a pictorial description of the Virtual Frame and its relationship to the WOI. NOTE!! The upd bit of the Integration Time MSB Register; Table 40 is used to indicate a change to cint[13:0]. Since multiple I2C writes may be needed to complete desired frame to frame integration time changes, the upd bit signals that all desired programming has been completed, and to apply these changes to the next frame captured. This prevents undesirable changes in integration time that may result from I2C writes that span the "End of Frame" boundary. This upd bit has to be toggled from its previous state in order for the new value of cint[13:0] to be accepted/updated by the sensor and take effect. i.e. If its previous state is "0", when writing a new cint value, first write cint[7:0] to the Integration Time LSB Register; Table 41, then write both cint [13:8] and "1" to the upd bit to the Integration Time MSB Register; Table 40. A virtual frame is the mechanism by which the user controls the integration time and frame time for the output Address 4Eh msb (7) 6 5 ImageMOS data stream. By adding additional rows or columns as `blanking' to the WOI to form the Virtual Frame, the user can control the amount of blanking in both horizontal and vertical space.(Table 42, "Virtual Frame Row Depth MSB Register," on page 55 Table 43, "Virtual Frame Row Depth LSB Register," on page 55Table 44, "Virtual Frame Column Width MSB Register," on page 56Table 45, "Virtual Frame Column Width LSB Register," on page 56) The user should be careful to create a Virtual Frame that is larger than the WOI. There is no logic in the sensor interface to prevent the user from defining a Virtual Frame smaller than the WOI. Therefore, pixel data may be lost. The Virtual Frame must be at least 1 row and 6 columns larger than the WOI. The Virtual Frame completely defines the integration time in CFRS. Any changes to the WOI or how the WOI is sampled has no effect on integration time. Integration Time MSB 4 3 2 1 Default 04h lsb (0) FUO Bit Number 7 6 upd Function FUO Integration Time Update Switch Integration Time cint[13] cint[12] cint[11] Description Factory Use Only cint[10] cint[9] cint[8] Reset State This bit has to change from its previous state everytime a new value is written to Integration Time ISB and the Integration Time LSB. 0 5-0 In conjunction with the Integration Time LSB (Table 41) Register, forms the 14-bit Integration Time cint[13:0]. Table 40. Integration Time MSB Register 000100b (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 54 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 4Fh msb (7) 6 5 Integration Time LSB 4 3 2 1 Default FFh lsb (0) cint[7] Bit Number 7-0 cint[6] Function Integration Time cint[5] cint[4] cint[3] Description cint[2] cint[1] cint[0] Reset State 11111111b CFRS and SFRS: 1280 Rows) In conjunction with the Integration Time ISB (Table 40) Register, forms the 14-bit Integration Time cint[13:0]. Integration Time = (cintd + 1) * Trow Table 41. Integration Time LSB Register Address 50h msb (7) 6 5 Virtual Frame Row Depth MSB 4 3 2 1 Default 04h lsb (0) x Bit Number 7-6 5-0 x Function Unused Virtual Row Depth vrd[13] vrd[12] vrd[11] Description vrd[10] vrd[9] vrd[8] Reset State xx 000100b Unused In conjunction with the CFRS and SFRS Virtual Frame Row Depth LSB (Table 43) Register, forms the 14-bit Virtual Frame Row Depth vrd[13:0]. Table 42. Virtual Frame Row Depth MSB Register Address 51h msb (7) 6 5 Virtual Frame Row Depth LSB 4 3 2 1 Default 27h lsb (0) vrd[7] Bit Number vrd[6] Function vrd[5] vrd[4] vrd[3] Description vrd[2] vrd[1] vrd[0] Reset State Table 43. Virtual Frame Row Depth LSB Register (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 55 MOTOROLA SEMICONDUCTOR TECHNICAL DATA Address 51h msb (7) 6 5 ImageMOS Virtual Frame Row Depth LSB 4 3 2 1 Default 27h lsb (0) vrd[7] 7-0 vrd[6] Virtual Row Depth vrd[5] vrd[4] vrd[3] vrd[2] vrd[1] vrd[0] 00100111b (1064 rows) In conjunction with the CFRS and SFRS Virtual Frame Row Depth MSB (Table 42) Register, forms the 14-bit Virtual Frame Row Depth vrd[13:0]. WOI is always top-left justified in Virtual Frame. vrdd minimum = wrdd + 1 Table 43. Virtual Frame Row Depth LSB Register Address 52h msb (7) 6 5 Virtual Frame Column Width MSB 4 3 2 1 Default 05h lsb (0) x Bit Number 7-6 5-0 x Function Unused Virtual Column Width vcw[13] vcw[12] vcw[11] Description vcw[10] vcw[9] vcw[8] Reset State xx 000101b Unused In conjunction with the CFRS and SFRS Virtual Frame Column Width LSB (Table 45) Register, forms the 14-bit Virtual Frame Column Width vcw[13:0]. Table 44. Virtual Frame Column Width MSB Register Address 53h msb (7) 6 5 Virtual Frame Column Width LSB 4 3 2 1 Default 13h lsb (0) vcw[7] Bit Number 7-0 vcw[6] Function Virtual Column Width vcw[5] vcw[4] vcw[3] Description vcw[2] vcw[1] vcw[0] Reset State 00010011b (1300 col.) In conjunction with the CFRS and SFRS Virtual Frame Column Width MSB (Table 44) Register, forms the 14-bit Virtual Frame Column Width vcw[13:0]. WOI is always top-left justified in Virtual Frame. vcwd minimum = wcwd + 11 Table 45. Virtual Frame Column Width LSB Register (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 56 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS is a parameter that cannot be easily identified by the common user). The VCLK Delay is defined as the time after the SOF signal is first initialized. The SOF & VCLK Signal Length Control Register, Table 48 , is used to define the size of the SOF and VCLK signals. In default, SOF is one row wide while VLCK is 64 MCLKs wide The SOF Delay Register; Table 46 and VCLK Delay Register; Table 47 are used to determine the time (clock) delay for the start of the two signals respectively. The SOF Delay is measured as the time after the start of the change of row address (Change of row address Address 54h msb (7) 6 5 4 SOF Delay 3 2 1 Default 4Ch lsb (0) sofd[7] Bit Number 7-0 sofd[6] Function SOF Delay sof[d5] sofd[4] sofd[3] Description sofd[2] sofd[1] sofd[0] Reset State 1001100b Delay= sofd[d] x 0.5 MCLKs (Note - Delay is relative to Internal Pixel Transfer Control) Table 46. SOF Delay Register Address 55h msb (7) 6 5 4 VCLK Delay 3 2 1 Default 02h lsb (0) vckd[7] Bit Number 7-0 vckd[6] Function VCLK Delay vckd[5] vckd[4] vckd[3] Description vckd[2] vckd[1] vckd[0] Reset State 00000010b Delay = vckd[d] x 0.5 MCLKs (Note - Delay is relative to Start Of Frame {SOF} signal) Table 47. VCLK Delay Register Address 56h msb (7) 6 5 SOF and VCLK Signal Length Control 4 3 2 1 Default Eh lsb (0) x Bit Number 3-2 x Function SOF Control x x sofc[3] Description sofc[2] vckc[1] vckc[0] Reset State 11b sof[3:2] = 00b = 1 MCLK Wide sof[3:2] = 01b = 8 MCLKs Wide sof[3:2] = 10b = 64 MCLKs Wide sof[3:2] = 11b = Full Row Wide Table 48. SOF & VCLK Signal Length Control Register (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 57 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 56h msb (7) 6 5 SOF and VCLK Signal Length Control 4 3 2 1 Default Eh lsb (0) x 1-0 x VCLK Control x x sofc[3] sofc[2] vckc[1] vckc[0] 10b vck[1:0] = 00b = 1 MCLK Wide vck[1:0] = 01b = 8 MCLKs Wide vck[1:0] = 10b = 64 MCLKs Wide vck[1:0] = 11b = Full Row Wide Table 48. SOF & VCLK Signal Length Control Register The Greycode and Readout Control Register; Table 49 allows the user to choose if the column and row addresses are to utilize Greycode address format or not. It also allows the user to select the user to select the direction of the row and column readout. The rrc when enabled causes the column data to be readout in the reverse direction as compared to the normal readout direction. The rrr when enabled causes the row data to be readout in the reverse direction as compared to the normal readout direction. The gcc bit when enabled causes the column addresses to be Greycoded. The gcr bit when enabled causes the column addresses to be Greycoded. Address 57h msb (7) 6 5 Greycode and Readout Control 4 3 2 1 Default 04h lsb (0) x Bit Number 7-4 3 x Function Unused Row Greycode Address Column Greycode Address Enable x x gcr Description gcc rrr rrc Reset State Unused 1b = Greycode addressing Enabled 0b = Binary Addressing 1b = Greycode addressing Enabled 0b = Binary Addressing 0b 2 1b Table 49. Greycode and Readout Control Register (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 58 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 57h msb (7) 6 5 Greycode and Readout Control 4 3 2 1 Default 04h lsb (0) x 1 x Row Readout x x gcr gcc rrr rrc 0b 1b = Reverse Readout (Top to Bottom) 0b = Normal Readout (Bottom to Top) 1b = Reverse Readout (Right to Left) 0b = Normal Readout (Left to Right Table 49. Greycode and Readout Control Register 0 Column Readout 0b The Internal Timing Control Register 1 (shs time definition); Table 50 and ,Internal Timing Control Register 2 (shr time definition); Table 51 are used to define the size of internal timing pulse widths. In default, both shs and shr are 6 MCLK's wide. A maximum of 64 MCLK`s can be programmed for the shs delay and another 64 MCLK`s for the shr delay, for a total 0f 128 MCLK`s. Note! writing 00h to either of these Registers will write a maximum timing delay of 64 MCLK`s. i.e. 00 = 64 MCLK Address 5Fh msb (7) 6 5 Internal Timing Control 4 3 2 1 Default 0Ah lsb (0) x Bit Number 7-6 5-0 x Function Unused shs shs[5] shs[4] shs[3] Description shs[2] shs[1] shs[0] Reset State xx 001010b Unused shs[5:0] = 000000b = 64 MCLKs Wide shs[5:0] = 000001b = 1d MCLKs Wide shs[5:0] = 000010b = 2d MCLKs Wide shs[5:0] = 000011b = 3d MCLKs Wide | | shs[5:0] = 111111b = 63d MCLKs Wide Table 50. Internal Timing Control Register 1 (shs time definition) (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 59 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 60h msb (7) 6 5 Internal Timing Control 4 3 2 1 Default 0Ah lsb (0) x Bit Number 7-6 5-0 x Function Unused shr shr[5] shr[4] shr[3] Description shr[2] shr[1] shr[0] Reset State xx 001010b Unused shr[5:0] = 000000b = 64 MCLKs Wide shr[5:0] = 000001b = 1d MCLKs Wide shr[5:0] = 000010b = 2d MCLKs Wide shr[5:0] = 000011b = 3d MCLKs Wide | | shr[5:0] = 111111b = 63d MCLKs Wide Table 51. Internal Timing Control Register 2 (shr time definition) The HCLK Delay Register; Table 52 allows the user to program the delay for the start of the HCLK signal. The delay is calculated in accordance to the result of inserting the value of the register into the following formula: Delay = ((hckd[d]-4)x 0.5) - 16 MCLKs Address 64h msb (7) 6 5 HCLK Control 4 3 2 1 Default 5Ch lsb (0) x Bit Number 7 6-3 FUO Function Unused FUO FUO FUO FUO Description hckd[2] hckd[1] hckd[0] Reset State x Unused Factory Use Only Table 52. HCLK Delay Register (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 60 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 64h msb (7) 6 5 HCLK Control 4 3 2 1 Default 5Ch lsb (0) x 2-0 FUO HCLK Delay FUO FUO FUO hckd[2] hckd[1] hckd[0] 100b Delay = ((hckd[d]-4)x 0.5) - 16 MCLKs Table 52. HCLK Delay Register The Pixel Data Stream Control Register allows the user to select how the output pixel data stream is encoded/formatted. The vcb bit allows the user to force all the Blanking data coming out of the A2D to be 0. The vcg bit allows the user to choose between encoded pixel data output stream or non-encoded pixel data output stream. The vcc bit allows the user to clip the output active pixel data to lie between 001 and 3FE The default mode (Normal Mode) has the SOF, HCLK, VCLK etc. signals being utilised to indicate the start of data and the end of data. (Figure 2, on page 7 and Figure 14, on page 20) Register Value = 00h Another mode, Video Mode is a mode where the SOF and Row start/end signals are encoded (contained) in the Active Pixel data stream. In addition, all data that is not a SOF, Row start/end, or Active pixel data are forced to 0. i.e. all Blanking data from the A2D are forced to 0. The following sequence identifies the signals below: (see Figure , on page 30) a) SOF (1st Row of Pixel Data) - "3FF x 4) b) Start of all other Rows - "3FF x 2" then "000 x 2" (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 61 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Register Value = 70 Address 65h msb (7) 6 Pixel Data Stream Signal Control Register 5 4 3 2 1 Default 00h lsb (0) x Bit Number 7 6 vcb Function Unused Vcode Blanking Vcode Sync Generation vsg vcc FUO Description FUO FUO FUO Reset State x Unused 1b = All blanking data will be forced to 0 0b = Blanking of Data 1b = Prefixes 3FF x 4 to beginning of active pixel data to indicate start of Row 1(SOF signal). Prefixes 3FF x 2 and then 000 x 2 to indicate start of all following Rows of data (VCLK) [Encoded data stream] 0b = Use of SOF, HCLK etc. signals for sync generation (No coded data stream) 1b = Will clip output data stream to values 001b to 3FEb 0b = No clipping of output data stream Factory Use Only Table 53. Pixel Data Stream Signal Control Register 0b 0b 5 4 Vcode Clipping FUO 0b 0000b 3-0 The FRC Definition Register; Table 54 allows the user to define the size of the dark rows to use as Clamping rows. The frcs bit identifies the starting position of the Clamping rows. i.e. If 4d is written to this register, the first clamped dark row would be the 4th row. The frcd bit identifies the FRC row depth. Allows the user to select the number of dark rows to clamp on. NOTE! Since there exists ONLY 11 dark rows the addition of FRC Row Depth + FRC Row Start should not be greater than 11, otherwise light rows would be clamped in the process. (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 62 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Address 67h msb (7) 6 5 FRC Definition 4 3 2 1 Default 24h lsb (0) x Bit Number 7 6 5-4 FUO Function Unused FUO FRC Row Depth FRC Row Start frcd[1] frcd[0] frcs[3] Description frcs[2] frcs[1] frcs[0] Reset State x Unused Factory Use Only Defines the number of Clamping Rows. NOTE!! The addition of FRC Row Depth + FRC Row Start should not be greater than 11d. Defines the first Clamping row. Defines the FRC starting point. Table 54. FRC Definition Register 10b 3-0 0100 (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 63 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 14.0 Electrical Characteristics ABSOLUTE MAXIMUM RATINGS1 (Voltages Referenced to VSS) Symbol VDD Vin Vout I I TSTG TL 1 Parameter DC Supply Voltage DC Input Voltage DC Output Voltage DC Current Drain per Pin, Any Single Input or Output DC Current Drain, VDD and VSS Pins Storage Temperature Range Lead Temperature (10 second soldering) Value -0.5 to 3.8 0.5 to VDD + 0.5 -0.5 to VDD + 0.5 50 100 -65 to +150 300 Unit V V V mA mA C C Maximum Ratings are those values beyond which damage to the device may occur. VSS = AVSS = DVSS = VSSO (DVSS = VSS of Digital circuit, AVSS = VSS of Analog Circuit) VDD = AVDD = DVDD = VDDO (DVDD = VDD of Digital circuit, AVDD = VDD of Analog Circuit) RECOMMENDED OPERATING CONDITIONS (to guarantee functionality; voltage referenced to VSS) Symbol VDD TA TJ Parameter DC Supply Voltage, VDD = 3.3V (Nominal) Commercial Operating Temperature Junction Temperature Min. 3.0 0 0 Max 3.6 40 55 Unit V C C Notes: - All parameters are characterized for DC conditions after thermal equilibrium has been established. - Unused inputs must always be tied to an appropriate logic level, e.g., either VSS or VDD. - This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit. - For proper operation it is recommended that Vin and Vout be constrained to the range VSS < (Vin or Vout) < VDD. DC ELECTRICAL CHARACTERISTICS (VDD = 3.3V 0.3V; VDD referenced to VSS; Ta = 0C to 40C) TA = 0C to 40C Symbol VIH VIL Iin Characteristic Input High Voltage Input Low Voltage Input Leakage Current, No Pull-up Resistor Vin = VDD or VSS Condition Min. 2.0 -0.3 -5 Max VDD+0.3 0.8 5 Unit V V A (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 64 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS IOH IOL VOH VOL IOZ IDD Output High Current Output Low Current Output High Voltage Output Low Voltage 3-State Output Leakage Current Maximum Standby Supply Current VDD = Min., VOH Min. = 0.8 * VDD VDD = Min., VOL Max = 0.4 V VDD = Min., IOH = -100A VDD = Min., IOL = 100A Output = High Impedance, Vout = VDD or VSS Iout = 0mA, Vin = VDD or VSS -3 3 VDD - 0.2 0.2 -10 0 10 15.0 mA mA V V A mA POWER DISSIPATION (VDD = 3.0V, VDD referenced to VSS; At = 25C) Symbol PSTDBY PAVG Parameter Standby Power Average Power Condition INIT Pin Logic High 13.5 MHz Operation Typ 100 250 Unit uW mW MCM20027 MONOCHROME CMOS IMAGE SENSOR ELECTRO-OPTICAL CHARACTERISTICS Symbol Esat QE PRNU Parameter Saturation Exposure Peak Quantum Efficiency (@550nm) Photoresponse Non-uniformity Typ 0.14 18 12 Unit J/cm % % pk-pk 2 Notes 1 2 3 Notes: 1.For = 550 nm wavelength. 2.Refer to typical values from Figure 3, MCM20027 nominal spectral response. 3.For a 100 x 100 pixel region under uniform illumination with output signal equal to 80% of saturation signal. MCM20027 COLOR CMOS IMAGE SENSOR ELECTRO-OPTICAL CHARACTERISTICS Symbol Esat QEr QEg QEb Parameter Saturation Exposure Red Peak Quantum Efficiency @ = 650 nm Green Peak Quantum Efficiency @ = 550 nm Blue Peak Quantum Efficiency @ = 450 nm Typ 0.3 12 11 8 Unit J/cm2 % % % Notes 1 2 2 2 Notes: 1.For = 550 nm wavelength. 2.Refer to typical values from Figure 3, MCM20027 nominal spectral response. CMOS IMAGE SENSOR CHARACTERISTICS Symbol Parameter Sensitivity Id DSNU CTE fH Xab Photodiode Dark Current Dark Signal Non-Uniformity (Entire Field) Pixel Charge Transfer Efficiency Horizontal Imager Frequency Blooming Margin - shuttered light Typ 1.8 0.2 0.4 0.9995 11.5 200 Unit V/lux-sec nA/cm2 % rms % MHz 1 4 2,3 Notes (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 65 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Notes: 1. Transfer efficiency of photosite 2. Xab represents the increase above the saturation-irradiance level (Hsat) that the device can be exposed to before blooming of the pixel will occur. 3. No column streaking 4. At 30fps VGA GENERAL Symbol ne- total DR Parameter Total System (equivalent) Noise Floor System Dynamic Range Typ 70 50 Unit e rms dB - Notes 1 Notes: 1.Includes amplifier noise, dark pattern noise and dark current shot noise at 13.5 MHz data rates. ANALOG SIGNAL PROCESSOR CHARACTERISTICS Analog to Digital Converter (ADC) Symbol Parameter Resolution VIN INL DNL fmax Input Dynamic Range 8 Min Typ 10 2.5 +1.0 +0.5 Max Units bits Vpp LSB LSB Integral Non-Linearity Differential Non-Linearity ADC Clock Rate 13.5 MHz Notes: 8 Effective differential signal dynamic range 9. INL & DNL test limits are adjusted to compensate for the effects of the LRC, DOVA and DPGA stages between teh EXT_VINS input and the input of the ADC. (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 66 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 15.0 MCM20027 Pin Definitions PIX_OUT9 PIX_OUT8 PIX_OUT7 40 PIX_OUT5 PIX_OUT6 39 38 PIX_OUT4 DVDD DVSS PIX_OUT2 PIX_OUT3 PIX_OUT0 PIX_OUT! note: pins 1 & 46 should be pulled down when not in use 41 42 37 36 35 33 34 32 31 Legend: P = VDD G = VSS I = Input O = Output D = Digital A = Analog MCLK VCLK HCLK SYNC STROBE SOF INIT DVDD DVSS AVSS AVDD CLRCA Top-View SDATA SCLK DVDD DVSS VSS_PIX VDD_PIX BIAS_IN AVDD AVSS CVBG EXTRESP 30 29 28 27 26 25 24 23 22 21 20 19 43 44 45 46 47 48 1 2 3 4 5 6 10 9 TST_VS 8 7 CLRCB TST_VR Connect to VDD See Section 8.6 for more information EXTRESR TN See Section 8.4 for more information Figure 20. MCM20027 Pin Definitions 12 11 14 13 CVREFM 15 17 16 18 EXT_VINS EXT_VINR AVDD AVSS VAGRTN VAG CVREFP VAGREF See Section 8.5 for more information (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 67 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Pin Pin No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 INIT DVDD DVSS AVSS AVDD CLRCA CLRCB TST_VR TST_VS Description Sensor Initialize Digital Power Digital Ground Analog Ground Analog Power Line Rate Clamp Output Line Rate Clamp Output Analog test reference Output Analog test signal Output Pin Power Type I P G G P O O O O I I G P O O I A I A I G P I A A A A D D A A Pin Pin No. Name 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 VDD_PIX VSS_PIX DVSS DVDD SCLK SDATA Description Pixel power Pixel ground Digital Ground Digital Power I2C Serial Clock I2C Serial Data Pin Power Type G P I/O I/O O O O O O P G O O O O O I O O I O O D D PIX_OUT0 Output bit 0 = 1 Weight PIX_OUT1 Output bit 1 = 2 Weight PIX_OUT2 Output bit 2 = 4 Weight PIX_OUT3 Output bit 3 = 8 Weight PIX_OUT4 Output bit 4 = 16 Weight DVDD DVSS Digital Power Digital Ground EXT_VINR Analog test reference Input EXT_VINS Analog test signal Input AVSS AVDD CVREFM CVREFP VAG VAGREF Analog Ground Analog Power Bias Reference Bottom Output Bias Reference Top Output Common Mode Cap Input Common Mode Caps Input D D PIX_OUT5 Output bit 5 = 32 Weight PIX_OUT6 Output bit 6 = 64 Weight PIX_OUT7 Output bit 7 = 128 Weight PIX_OUT8 Output bit 8 = 256 Weight PIX_OUT9 Output bit 9 = 512 Weight MCLK VCLK HCLK SYNC STROBE SOF Master Clock Line Sync Pixel Sync Sensor Sync Signal Strobe signal Start Of Frame VAGRETN Common Mode Cap Return EXTRESR EXTRES Return TN EXTRES CVBG AVSS AVDD BIAS_IN External Bias Resistor Input Bandgap Voltage Testpoint Analog Ground Analog Power Pixel row 1046/7 inj Bias in Table 55. MCM20027 Pin Definitions I P G O D A I/O INPUT POWER GROUND OUTPUT DIGITAL ANALOG BIDIRECTIONAL (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 68 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 16.0 MCM20027 Packaging Information Figure 21. 48 Terminal ceramic leadless chip carrier (bottom view) Dim A B C D E F G H J K R R1 0.033 0.555 0.525 Min(Inches) 0.555 0.525 --0.016 0.054 0.075 0.040 BSC 0.047 0.572 0.545 Max(Inches) 0.572 0.545 0.09362 0.024 0.068 0.095 0.0075 (Radius) 0.0075 (Radius) (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 69 MOTOROLA SEMICONDUCTOR TECHNICAL DATA PIX_OUT7 PIX_OUT9 PIX_OUT8 PIX_OUT5 PIX_OUT6 VSS PIX_OUT3 VDD PIX_OUT4 PIX_OUT2 PIX_OUT1 PIX_OUT0 42 41 40 39 38 37 36 35 34 33 32 31 1 MCLK 43 44 45 2 3 4 5 67 89 10 11 12 13 14 MOT INC. M 30 SDATA 60 15 16 VCLK 59 58 17 18 29 SCLK 28 VDD 27 VSS 26 VSS_PIX 25 VDD_PIX 24 BIAS_IN 23 VDDA 22 VSSA 21 CVBG HCLK 57 SYNC 46 56 Y-axis Offset +1226m (~48 mil) X-Offset: +52m (~2mil) Active Pixel Array Center 19 20 STROBE 47 55 X-axis Offset +182m (~7 mil) Y-Offset: +400m (~16mil) 21 SOF 48 54 22 INIT Pin VDD 1 2 3 4 5 6 23 53 52 Die Placement positional tolerance 200um (+/- 4 mil) 24 25 VSS 51 50 26 27 49 48 28 VSSA VDDA 47 46 45 29 30 44 43 42 41 40 39 38 37 36 35 34 33 32 31 K06K 20 EXTRESP 19 VSSA CLRCA 7 8 9 10 11 12 13 14 15 16 17 VSSA 18 VAGREF CLRCB TST_VR TST_VS EXT_VINR EXT_VINS VSSA VDDA CVREFM CVREFP VAG Figure 23. Center of the focal plane array with respect to the die cavity (top view) Notes: 1. Dimensions are in inches. 2. Interpret dimensions and tolerances per ASME Y14.5-1994 (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS A F - Lid Seal thickness G B J D E - Die Attach thickness C - Die H Dimension Description Nominal Metric (mm) min 0.50000 0.99060 0.70500 0.38100 0.01270 0.00635 0.67575 0.17575 1.09870 1.87795 1.70180 max 0.60000 1.24460 0.74500 0.48260 0.07620 0.05080 1.17770 0.57770 1.30380 2.37800 1.39700 Nominal English (inches) min 0.01969 0.03900 0.02776 0.01500 0.00050 0.00025 0.02660 0.00692 0.04326 0.07393 0.06700 max 0.02362 0.04900 0.02933 0.01900 0.00300 0.00200 0.04637 0.02274 0.05133 0.09362 0.05500 A B C D E F G H J Glass (Thickness) Cavity (Depth) Die - Si (Thickness) Bottom Layer (Thickness) Die Attach - bondline (Thickness) Glass Attach - bondline (Thickness) Imager to Lid - outer surface (d) Imager to Lid - inner surface (d) Imager to seating plane - of pkg Pkg (Th - total) Base (Th) 0.55000 1.11760 0.72500 0.43180 0.02540 0.02540 0.94260 0.39260 1.18220 2.12480 1.54940 0.02165 0.04400 0.02854 0.01700 0.00100 0.00100 0.03711 0.01546 0.04654 0.08365 0.06100 Note: The package sketch is representative and does not necessarily reflect exact scale and relative feature sizes. Reference Notes: 1mil = 25.4um 1mm = 39.37mil Figure 22. 48 Terminal ceramic leadless chip carrier (z-direction view) (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 71 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS 17.0 MCM20027 Typical Connection Below you will find a schematic illustrating a typical connection of an MCM20027 CMOS sensor. One can use this as a reference when connecting the sensor with another external device such as an image processor, SDRAM etc.This schematic also illustrates the connection of the required passives on the sensor. M ASTE C K R LOC STROBE INITIALIZE START DATA CAPTURE I2C D _ ATA I2C _CLK 43 C 47 M LK 1 STROBE INIT 46 SYN C 30 D 29 S ATA SCLK 21 10 CVBG 11 EXT_VINR EXT_VINS 18 RF 17 VAG E R TN 16 VAG E VAG .1uf 9 8 TST_VS 14 TST_VR 15 CVREFM CVREFP DD VD 2 VD 28 D D VD 36 D D VD 24 D D BIAS_IN D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 H LK C VCLK SF O CR A LC CR B LC 31 32 33 34 35 38 39 40 41 42 45 44 48 6 7 PIXE D L ATA 0 PIXE D L ATA 1 PIXE D L ATA 2 PIXE D L ATA 3 PIXE D L ATA 4 PIXE D L ATA 5 PIXE D L ATA 6 PIXE D L ATA 7 PIXE D L ATA 8 PIXE D L ATA 9 D VALID ATA HORIZONTALSYNC STARTOFFRAME .1uf +3.3V B AD E 20 EXTRES 19 E XTRESGN D 25 VD D _PIX 23 AVDD 5 AVDD 13 AVDD 27K 4.7/25 .01uf .01uf .01uf .01uf 3 37 DVSS 27 DVSS DVSS M 20027IB GND GND 26 VSS_P 22 IX AVSS 12 AVSS 4 AVSS AN GD .1uf .1uf GND .1uf .1uf +3.3V B AD E .01uf GND AN GD AN GD AN AN AN GD GD GD .01uf .01uf .01uf 4.7/25 AVD D GD N (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 72 MOTOROLA SEMICONDUCTOR TECHNICAL DATA ImageMOS Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MFax is a trademark of Motorola, Inc. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver Colorado 80217. 1-800-441-2447 or 303-675-2140 MFaxTM: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 HOME PAGE:http://motorola.com/sps/ JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 ELECTRO STATIC DISCHARGE WARNING: This device is sensitive to electrostatic discharge (ESD).ESD immunity meets Human Body Model (HBM) < 1500 V and Machine Model (MM) < 150 V Additional ESD data upon request. When handling this part, proper ESD precautions should be followed to avoid exposing the device to discharges which may be detrimental to its immediate performance and/or reduce the parts expected lifetime.. (c) MOTOROLA, INC. 2001 Revision 8.0 - 28 November 2001 : MCM20027 73 This datasheet has been download from: www..com Datasheets for electronics components. |
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